top_watch.tan.rpt
来自「60秒秒表设计」· RPT 代码 · 共 300 行 · 第 1/5 页
RPT
300 行
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[3] ; div192:div1|count96[7] ; clk768 ; clk768 ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[4] ; div192:div1|count96[7] ; clk768 ; clk768 ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[5] ; div192:div1|count96[7] ; clk768 ; clk768 ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[7] ; div192:div1|count96[7] ; clk768 ; clk768 ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[6] ; div192:div1|count96[7] ; clk768 ; clk768 ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[0] ; div192:div1|count96[6] ; clk768 ; clk768 ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[1] ; div192:div1|count96[6] ; clk768 ; clk768 ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[2] ; div192:div1|count96[6] ; clk768 ; clk768 ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[3] ; div192:div1|count96[6] ; clk768 ; clk768 ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[4] ; div192:div1|count96[6] ; clk768 ; clk768 ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[5] ; div192:div1|count96[6] ; clk768 ; clk768 ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[7] ; div192:div1|count96[6] ; clk768 ; clk768 ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[6] ; div192:div1|count96[6] ; clk768 ; clk768 ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[0] ; div192:div1|clk4 ; clk768 ; clk768 ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[1] ; div192:div1|clk4 ; clk768 ; clk768 ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[2] ; div192:div1|clk4 ; clk768 ; clk768 ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[3] ; div192:div1|clk4 ; clk768 ; clk768 ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[4] ; div192:div1|clk4 ; clk768 ; clk768 ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[5] ; div192:div1|clk4 ; clk768 ; clk768 ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[7] ; div192:div1|clk4 ; clk768 ; clk768 ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[6] ; div192:div1|clk4 ; clk768 ; clk768 ; None ; None ; 8.000 ns ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|clk4 ; div192:div1|clk4 ; clk768 ; clk768 ; None ; None ; 8.000 ns ;
+-------+----------------------------------+------------------------+------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------+------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------+------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 45.45 MHz ( period = 22.000 ns ) ; counter:counts|count100:count_1|low1[3] ; dtlatch:dtlatch1|sel_din[5] ; clk ; clk ; None ; None ; 17.000 ns ;
; N/A ; 45.45 MHz ( period = 22.000 ns ) ; counter:counts|count100:count_1|high1[0] ; dtlatch:dtlatch1|sel_din[5] ; clk ; clk ; None ; None ; 17.000 ns ;
; N/A ; 45.45 MHz ( period = 22.000 ns ) ; counter:counts|count100:count_1|high1[1] ; dtlatch:dtlatch1|sel_din[5] ; clk ; clk ; None ; None ; 17.000 ns ;
; N/A ; 45.45 MHz ( period = 22.000 ns ) ; counter:counts|count100:count_1|high1[2] ; dtlatch:dtlatch1|sel_din[5] ; clk ; clk ; None ; None ; 17.000 ns ;
; N/A ; 45.45 MHz ( period = 22.000 ns ) ; counter:counts|count100:count_1|high1[3] ; dtlatch:dtlatch1|sel_din[5] ; clk ; clk ; None ; None ; 17.000 ns ;
; N/A ; 45.45 MHz ( period = 22.000 ns ) ; counter:counts|count60:count_2|low2[0] ; dtlatch:dtlatch1|sel_din[5] ; clk ; clk ; None ; None ; 17.000 ns ;
; N/A ; 45.45 MHz ( period = 22.000 ns ) ; counter:counts|count60:count_2|low2[1] ; dtlatch:dtlatch1|sel_din[5] ; clk ; clk ; None ; None ; 17.000 ns ;
; N/A ; 45.45 MHz ( period = 22.000 ns ) ; counter:counts|count60:count_2|low2[2] ; dtlatch:dtlatch1|sel_din[5] ; clk ; clk ; None ; None ; 17.000 ns ;
; N/A ; 45.45 MHz ( period = 22.000 ns ) ; counter:counts|count60:count_2|low2[3] ; dtlatch:dtlatch1|sel_din[5] ; clk ; clk ; None ; None ; 17.000 ns ;
; N/A ; 45.45 MHz ( period = 22.000 ns ) ; counter:counts|count60:count_2|lpm_counter:high2_rtl_0|dffs[0] ; dtlatch:dtlatch1|sel_din[5] ; clk ; clk ; None ; None ; 17.000 ns ;
; N/A ; 45.45 MHz ( period = 22.000 ns ) ; counter:counts|count60:count_2|lpm_counter:high2_rtl_0|dffs[1] ; dtlatch:dtlatch1|sel_din[5] ; clk ; clk ; None ; None ; 17.000 ns ;
; N/A ; 45.45 MHz ( period = 22.000 ns ) ; counter:counts|count60:count_2|lpm_counter:high2_rtl_0|dffs[2] ; dtlatch:dtlatch1|sel_din[5] ; clk ; clk ; None ; None ; 17.000 ns ;
; N/A ; 45.45 MHz ( period = 22.000 ns ) ; counter:counts|count60:count_2|lpm_counter:high2_rtl_0|dffs[3] ; dtlatch:dtlatch1|sel_din[5] ; clk ; clk ; None ; None ; 17.000 ns ;
; N/A ; 45.45 MHz ( period = 22.000 ns ) ; counter:counts|count60:count_2|carry ; dtlatch:dtlatch1|sel_din[5] ; clk ; clk ; None ; None ; 17.000 ns ;
; N/A ; 45.45 MHz ( period = 22.000 ns ) ; counter:counts|count100:count_1|low1[0] ; dtlatch:dtlatch1|sel_din[6] ; clk ; clk ; None ; None ; 17.000 ns ;
; N/A ; 45.45 MHz ( period = 22.000 ns ) ; counter:counts|count100:count_1|low1[1] ; dtlatch:dtlatch1|sel_din[6] ; clk ; clk ; None ; None ; 17.000 ns ;
; N/A ; 45.45 MHz ( period = 22.000 ns ) ; counter:counts|count100:count_1|low1[2] ; dtlatch:dtlatch1|sel_din[6] ; clk ; clk ; None ; None ; 17.000 ns ;
; N/A ; 45.45 MHz ( period = 22.000 ns ) ; counter:counts|count100:count_1|low1[3] ; dtlatch:dtlatch1|sel_din[6] ; clk ; clk ; None ; None ; 17.000 ns ;
; N/A ; 45.45 MHz ( period = 22.000 ns ) ; counter:counts|count100:count_1|high1[0] ; dtlatch:dtlatch1|sel_din[6] ; clk ; clk ; None ; None ; 17.000 ns ;
; N/A ; 45.45 MHz ( period = 22.000 ns ) ; counter:counts|count100:count_1|high1[1] ; dtlatch:dtlatch1|sel_din[6] ; clk ; clk ; None ; None ; 17.000 ns ;
; N/A ; 45.45 MHz ( period = 22.000 ns ) ; counter:counts|count100:count_1|high1[2] ; dtlatch:dtlatch1|sel_din[6] ; clk ; clk ; None ; None ; 17.000 ns ;
; N/A ; 45.45 MHz ( period = 22.000 ns ) ; counter:counts|count100:count_1|high1[3] ; dtlatch:dtlatch1|sel_din[6] ; clk ; clk ; None ; None ; 17.000 ns ;
; N/A ; 45.45 MHz ( period = 22.000 ns ) ; counter:counts|count60:count_2|low2[0] ; dtlatch:dtlatch1|sel_din[6] ; clk ; clk ; None ; None ; 17.000 ns ;
; N/A ; 45.45 MHz ( period = 22.000 ns ) ; counter:counts|count60:count_2|low2[1] ; dtlatch:dtlatch1|sel_din[6] ; clk ; clk ; None ; None ; 17.000 ns ;
; N/A ; 45.45 MHz ( period = 22.000 ns ) ; counter:counts|count60:count_2|low2[2] ; dtlatch:dtlatch1|sel_din[6] ; clk ; clk ; None ; None ; 17.000 ns ;
; N/A ; 45.45 MHz ( period = 22.000 ns ) ; counter:counts|count60:count_2|low2[3] ; dtlatch:dtlatch1|sel_din[6] ; clk ; clk ; None ; None ; 17.000 ns ;
; N/A ; 45.45 MHz ( period = 22.000 ns ) ; counter:counts|count60:count_2|lpm_counter:high2_rtl_0|dffs[0] ; dtlatch:dtlatch1|sel_din[6] ; clk ; clk ; None ; None ; 17.000 ns ;
; N/A ; 45.45 MHz ( period = 22.000 ns ) ; counter:counts|count60:count_2|lpm_counter:high2_rtl_0|dffs[1] ; dtlatch:dtlatch1|sel_din[6] ; clk ; clk ; None ; None ; 17.000 ns ;
; N/A ; 45.45 MHz ( period = 22.000 ns ) ; counter:counts|count60:count_2|lpm_counter:high2_rtl_0|dffs[2] ; dtlatch:dtlatch1|sel_din[6] ; clk ; clk ; None ; None ; 17.000 ns ;
; N/A ; 45.45 MHz ( period = 22.000 ns ) ; counter:counts|count60:count_2|lpm_counter:high2_rtl_0|dffs[3] ; dtlatch:dtlatch1|sel_din[6] ; clk ; clk ; None ; None ; 17.000 ns ;
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