top_watch.tan.rpt

来自「60秒秒表设计」· RPT 代码 · 共 300 行 · 第 1/5 页

; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk768          ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk768'                                                                                                                                                                                  ;
+-------+----------------------------------+------------------------+------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)             ; From                   ; To                     ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+----------------------------------+------------------------+------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[0] ; div192:div1|count96[0] ; clk768     ; clk768   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[0] ; div192:div1|count96[1] ; clk768     ; clk768   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[1] ; div192:div1|count96[1] ; clk768     ; clk768   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[0] ; div192:div1|count96[2] ; clk768     ; clk768   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[1] ; div192:div1|count96[2] ; clk768     ; clk768   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[2] ; div192:div1|count96[2] ; clk768     ; clk768   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[0] ; div192:div1|count96[3] ; clk768     ; clk768   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[1] ; div192:div1|count96[3] ; clk768     ; clk768   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[2] ; div192:div1|count96[3] ; clk768     ; clk768   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[3] ; div192:div1|count96[3] ; clk768     ; clk768   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[0] ; div192:div1|count96[4] ; clk768     ; clk768   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[1] ; div192:div1|count96[4] ; clk768     ; clk768   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[2] ; div192:div1|count96[4] ; clk768     ; clk768   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[3] ; div192:div1|count96[4] ; clk768     ; clk768   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[4] ; div192:div1|count96[4] ; clk768     ; clk768   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[0] ; div192:div1|count96[5] ; clk768     ; clk768   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[1] ; div192:div1|count96[5] ; clk768     ; clk768   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[2] ; div192:div1|count96[5] ; clk768     ; clk768   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[3] ; div192:div1|count96[5] ; clk768     ; clk768   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[4] ; div192:div1|count96[5] ; clk768     ; clk768   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[5] ; div192:div1|count96[5] ; clk768     ; clk768   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[7] ; div192:div1|count96[5] ; clk768     ; clk768   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[6] ; div192:div1|count96[5] ; clk768     ; clk768   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[0] ; div192:div1|count96[7] ; clk768     ; clk768   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[1] ; div192:div1|count96[7] ; clk768     ; clk768   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; div192:div1|count96[2] ; div192:div1|count96[7] ; clk768     ; clk768   ; None                        ; None                      ; 8.000 ns                ;