cpu.v

这个文件中使用verilog hdl简单的利用基本运算实现了微型的cpu设计开发过程

// clk      : -_-_-_-_-_-_-_-_-_
// clk2     : _--__--__--__--__-
// fetch    : _----____----____-
// phase    : 701234567012345670
// alu_clock: -------_-------_--
// mem_rd   : __---_???_---_???_
// daten    : _______??______??_

`resetall
`include "defines.v"

module cpu      (
                halt  ,
                clk   ,
                clk2  ,
                fetch ,
                rst_
                );

output          halt  ;
input           clk   ;
input           clk2  ;
input           fetch ;
input           rst_  ;

wire    [7:0]   data, alu_out, accum;
wire    [4:0]   pc_addr, ir_addr, addr;
wire    [2:0]   opcode;
wire     mem_rd;

register ac     (				
                .out     (accum         ),
                .data    (alu_out       ),
                .clk     (clk           ),
                .enable     (load_ac       ),
                .reset_    (rst_          ) 
                );

register ir     (				
                .out     ({opcode,ir_addr}),
                .data    (data          ),
                .clk     (clk           ),
                .enable     (load_ir       ),
                .reset_    (rst_          ) 
                );

counter  pc     (				
                .cnt     (pc_addr       ),
                .data    (ir_addr       ),
                .clk     (inc_pc        ),
                .load    (load_pc       ),
                .rst_    (rst_          ) 
                );

assign alu_clk = clk | clk2 | fetch;

alu      alu1   (				
                .out    (alu_out        ),
                .zero   (zero           ),
                .clk    (alu_clk        ),
                .accum  (accum          ),
                .data   (data           ),
                .opcode (opcode         ) 
                );


assign daten_ = fetch | mem_rd | clk2;

assign data = daten_? 8'bz : alu_out;

scalable_mux #5 smx(				
                .out     (addr          ),
                .in_a    (pc_addr       ),
                .in_b    (ir_addr       ),
                .sel_a   (fetch         ) 
                );

memory      mem1   (				
                .data    (data          ),
                .addr    (addr          ),
                .read    (mem_rd        ),
                .write   (mem_wr        ) 
                );

control  cntl   (				
                .load_ac (load_ac       ),
                .mem_rd  (mem_rd        ),
                .mem_wr  (mem_wr        ),
                .inc_pc  (inc_pc        ),
                .load_pc (load_pc       ),
                .load_ir (load_ir       ),
                .halt    (halt          ),
                .opcode  (opcode        ),
                .zero    (zero          ),
                .clk     (clk           ),
                .clk2    (clk2          ),
                .fetch   (fetch         ),
                .rst_    (rst_          ) 
                );

endmodule