alu.v

来自「这个文件中使用verilog hdl简单的利用基本运算实现了微型的cpu设计开发」· Verilog 代码 · 共 38 行

`include "defines.v"
module alu
	(
	out    ,
	zero   ,
	clk    ,
	accum  ,
	data   ,
	opcode   
	);

output [7:0] out    ;
output       zero   ;
input        clk    ;
input  [7:0] accum  ;
input  [7:0] data   ;
input  [2:0] opcode ;
reg    [7:0] out    ;
reg          zero   ;
 
  always @(negedge clk)
    case ( opcode )
      `ALUADD : out <= accum + data;
      `ALUAND : out <= accum & data;
      `ALUXOR : out <= accum ^ data;
      `PASSD  : out <=         data;
      `PASS1,
      `PASS2,
      `PASS3,
      `PASS4  : out <= accum;
      default : out <= 8'bx;
    endcase

  always @(accum)
    zero = ~(|accum);

endmodule