control.v

来自「这个文件中使用verilog hdl简单的利用基本运算实现了微型的cpu设计开发」· Verilog 代码 · 共 96 行

`include "defines.v"
module control  (
                load_ac ,
                mem_rd  ,
                mem_wr  ,
                inc_pc  ,
                load_pc ,
                load_ir ,
                halt    ,
                opcode  ,
                zero    ,
                clk     ,
                clk2    ,
                fetch   ,
                rst_   
                );

output          load_ac ;
output          mem_rd  ;
output          mem_wr  ;
output          inc_pc  ;
output          load_pc ;
output          load_ir ;
output          halt    ;
input   [2:0]   opcode  ;
input           zero    ;
input           clk     ;
input           clk2    ;
input           fetch   ;
input           rst_    ;

reg     [2:0]   phase   ;

  always @ ( clk )
    if ( !rst_ )
      phase <= 0;
    else
      if ( clk && clk2 && fetch || phase!=0 )
        phase <= phase+1;

assign load_ir =
            phase==2
         || phase==3
         ;

assign halt =
            phase==4 && opcode==`HLT
         ;

assign inc_pc =
            phase==4
         || phase==6 && opcode==`SKZ && zero
         || phase==7 && opcode==`SKZ && zero
         || phase==7 && opcode==`JMP
         ;

assign mem_rd =
            phase==1
         || phase==2
         || phase==3
         || phase==5 && opcode==`ADD
         || phase==5 && opcode==`AND
         || phase==5 && opcode==`XOR
         || phase==5 && opcode==`LDA
         || phase==6 && opcode==`ADD
         || phase==6 && opcode==`AND
         || phase==6 && opcode==`XOR
         || phase==6 && opcode==`LDA
         || phase==7 && opcode==`ADD
         || phase==7 && opcode==`AND
         || phase==7 && opcode==`XOR
         || phase==7 && opcode==`LDA
         ;

assign load_ac =
            phase==6 && opcode==`ADD
         || phase==6 && opcode==`AND
         || phase==6 && opcode==`XOR
         || phase==6 && opcode==`LDA
         || phase==7 && opcode==`ADD
         || phase==7 && opcode==`AND
         || phase==7 && opcode==`XOR
         || phase==7 && opcode==`LDA
         ;

assign load_pc =
            phase==6 && opcode==`JMP
         || phase==7 && opcode==`JMP
         ;

assign mem_wr =
            phase==7 && opcode==`STO
         ;

endmodule