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这个文件中使用verilog hdl简单的利用基本运算实现了微型的cpu设计开发过程

# do sim.do 
# ** Warning: (vlib-34) Library already exists at "work".
# Modifying C:\altera\72\modelsim_ae\win32aloem/../modelsim.ini
# Model Technology ModelSim ALTERA vlog 6.1g Compiler 2006.08 Aug 12 2006
# -- Compiling module alu
# -- Compiling module clockgen
# -- Compiling module control
# -- Compiling module counter
# -- Compiling module cpu
# -- Compiling module memory
# -- Compiling module register
# -- Compiling module scalable_mux
# -- Compiling module cpu_test
# 
# Top level modules:
# 	cpu_test
# vsim -novopt cpu_test 
# Loading work.cpu_test
# Loading work.clockgen
# Loading work.cpu
# Loading work.register
# Loading work.counter
# Loading work.alu
# Loading work.scalable_mux
# Loading work.memory
# Loading work.control
run -all
# 
# ****************************************
# THE FOLLOWING DEBUG TASKS ARE AVAILABLE:
# 1- The basic CPU diagnostic.            
# 2- The advanced CPU diagnostic.         
# 3- The Fibonacci program.               
# ****************************************
# 
# Please Change test_number's value
# 
# CPUtest1 - BASIC CPU DIAGNOSTIC PROGRAM 
# 
# THIS TEST SHOULD HALT WITH THE PC AT 17 hex
# 
#      TIME       PC    INSTR    OP   ADR   DATA
# 
#   ----------    --    -----    --   ---   ----
# 
#      95.0 ns    00    JMP      7    00     fe
#     175.0 ns    1e    JMP      7    1e     e3
#     255.0 ns    03    LDA      5    03     ba
#     335.0 ns    04    SKZ      1    04     20
#     415.0 ns    06    LDA      5    06     bb
#     495.0 ns    07    SKZ      1    07     20
#     575.0 ns    08    JMP      7    08     ea
#     655.0 ns    0a    STO      6    0a     dc
#     735.0 ns    0b    LDA      5    0b     ba
#     815.0 ns    0c    STO      6    0c     dc
#     895.0 ns    0d    LDA      5    0d     bc
#     975.0 ns    0e    SKZ      1    0e     20
#    1055.0 ns    10    XOR      4    10     9b
#    1135.0 ns    11    SKZ      1    11     20
#    1215.0 ns    12    JMP      7    12     f4
#    1295.0 ns    14    XOR      4    14     9b
#    1375.0 ns    15    SKZ      1    15     20
#    1455.0 ns    17    HLT      0    17     00
# 
# CPU TEST PASSED
# ** Note: $finish    : cpu_test.v(106)
#    Time: 1470 ns  Iteration: 1  Instance: /cpu_test
# Break at cpu_test.v line 106