_primary.vhd

两条5级的并行流水线

library verilog;
use verilog.vl_types.all;
entity RegGroup32v3 is
    port(
        QA1             : out    vl_logic_vector(31 downto 0);
        QA2             : out    vl_logic_vector(31 downto 0);
        QB1             : out    vl_logic_vector(31 downto 0);
        QB2             : out    vl_logic_vector(31 downto 0);
        DA              : in     vl_logic_vector(31 downto 0);
        DB              : in     vl_logic_vector(31 downto 0);
        clk_up          : in     vl_logic;
        selRA1          : in     vl_logic_vector(4 downto 0);
        selRA2          : in     vl_logic_vector(4 downto 0);
        selRB1          : in     vl_logic_vector(4 downto 0);
        selRB2          : in     vl_logic_vector(4 downto 0);
        selWA           : in     vl_logic_vector(4 downto 0);
        selWB           : in     vl_logic_vector(4 downto 0);
        enable1         : in     vl_logic;
        enable2         : in     vl_logic;
        clr             : in     vl_logic;
        sys_0           : in     vl_logic
    );
end RegGroup32v3;