_primary.vhd

来自「两条5级的并行流水线」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity ToJmp is
    port(
        IRDec           : in     vl_logic_vector(15 downto 0);
        Flag            : in     vl_logic_vector(3 downto 0);
        Jmp             : out    vl_logic
    );
end ToJmp;