_primary.vhd

来自「两条5级的并行流水线」· VHDL 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity IR_PC is
    port(
        Dout            : out    vl_logic_vector(31 downto 0);
        Din             : in     vl_logic_vector(31 downto 0);
        Ld              : in     vl_logic;
        Inc8            : in     vl_logic;
        clr             : in     vl_logic;
        clk             : in     vl_logic
    );
end IR_PC;