_primary.vhd

来自「两条5级的并行流水线」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity Mult16_M is
    port(
        result          : out    vl_logic_vector(31 downto 0);
        Busy            : out    vl_logic;
        a               : in     vl_logic_vector(15 downto 0);
        b               : in     vl_logic_vector(15 downto 0);
        Load            : in     vl_logic;
        clear_0         : in     vl_logic;
        clk_up          : in     vl_logic
    );
end Mult16_M;