_primary.vhd

来自「两条5级的并行流水线」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity Adder8 is
    port(
        \out\           : out    vl_logic_vector(7 downto 0);
        cout            : out    vl_logic;
        \of\            : out    vl_logic;
        Pout            : out    vl_logic;
        Gout            : out    vl_logic;
        a               : in     vl_logic_vector(7 downto 0);
        b               : in     vl_logic_vector(7 downto 0);
        cin             : in     vl_logic
    );
end Adder8;