_primary.vhd

来自「两条5级的并行流水线」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity SuperCPU is
    port(
        reset           : in     vl_logic;
        clk             : in     vl_logic;
        INTR            : in     vl_logic;
        IntType         : in     vl_logic_vector(7 downto 0)
    );
end SuperCPU;