_primary.vhd

来自「两条5级的并行流水线」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity RegFlag is
    port(
        FlagQ           : out    vl_logic_vector(31 downto 0);
        IRDecA          : in     vl_logic_vector(15 downto 0);
        IRDecB          : in     vl_logic_vector(15 downto 0);
        FlagA           : in     vl_logic_vector(3 downto 0);
        FlagB           : in     vl_logic_vector(3 downto 0);
        clk             : in     vl_logic;
        clr             : in     vl_logic
    );
end RegFlag;