_primary.vhd

来自「两条5级的并行流水线」· VHDL 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity MUX4 is
    port(
        Q               : out    vl_logic;
        sel             : in     vl_logic_vector(1 downto 0);
        D3              : in     vl_logic;
        D2              : in     vl_logic;
        D1              : in     vl_logic;
        D0              : in     vl_logic
    );
end MUX4;