_primary.vhd

来自「两条5级的并行流水线」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity MUX32sp is
    port(
        Q               : out    vl_logic;
        sel             : in     vl_logic_vector(4 downto 0);
        D               : in     vl_logic_vector(31 downto 0)
    );
end MUX32sp;