trigger2.v

ＦＰＧＡ实现数字滤波器

module trigger2(oe,pout,yout);
    input oe;
    input[20:0] pout;
    output[15:0] yout;
    reg[15:0] yout;
    always @(posedge oe)
    begin yout=pout[15:0]; end
endmodule