alu.v

ＦＰＧＡ实现数字滤波器

module alu(hxi,hxin,hout);
    input[17:0] hxi;
    input[20:0] hxin;
    output[20:0] hout;
    wire[20:0] hxii;
    wire[20:0] hout;
    wire c0,c11,c10,cout;
    wire[3:0] hout1,hout0; 
      
    assign hxii[20:18]={3{hxi[17]}};
    assign hxii[17:0]=hxi[17:0];
    adder16 hxadder16(hout[15:0],c0,hxii[15:0],hxin[15:0],0);
    adder4 hxadder41(hout1[3:0],c11,hxii[19:16],hxin[19:16],1);
    adder4 hxadder40(hout0[3:0],c10,hxii[19:16],hxin[19:16],0);
    assign hout[19:16]=c0?hout1[3:0]:hout0[3:0];
    assign {cout,hout[20]}=hxii[20]+hxin[20]+(c0?c11:c10);
    
endmodule