counter.v

verilog语言写的简单八位处理器。有8个模块

module counter(PC_ADDR,IR_ADDR,LOAD,CLOCK,RST);
    output[11:0]PC_ADDR;
    input[11:0]IR_ADDR;
    input LOAD,CLOCK,RST;
    reg[11:0]PC_ADDR;
    always@(posedge CLOCK or posedge RST)
       begin
           if(RST)   
              PC_ADDR<=12'b0000_0000_0000;
           else
           if(LOAD)
              PC_ADDR<=IR_ADDR;
           else
           PC_ADDR<=PC_ADDR+1;
       end
endmodule