hdlc.tan.qmsg

该工程是基于verilog hdl 语言编写的帧传输协议HDLC帧的发送端代码

{ "Info" "ITDB_FULL_TPD_RESULT" "ept en1 11.368 ns Longest " "Info: Longest tpd from source pin \"ept\" to destination pin \"en1\" is 11.368 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns ept 1 PIN PIN_41 9 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_41; Fanout = 9; PIN Node = 'ept'" {  } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { ept } "NODE_NAME" } "" } } { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.295 ns) + CELL(0.454 ns) 5.884 ns control:control1\|always0~271 2 COMB LC_X20_Y7_N6 2 " "Info: 2: + IC(4.295 ns) + CELL(0.454 ns) = 5.884 ns; Loc. = LC_X20_Y7_N6; Fanout = 2; COMB Node = 'control:control1\|always0~271'" {  } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "4.749 ns" { ept control:control1|always0~271 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.336 ns) + CELL(0.454 ns) 6.674 ns control:control1\|comb~0 3 COMB LC_X20_Y7_N4 2 " "Info: 3: + IC(0.336 ns) + CELL(0.454 ns) = 6.674 ns; Loc. = LC_X20_Y7_N4; Fanout = 2; COMB Node = 'control:control1\|comb~0'" {  } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "0.790 ns" { control:control1|always0~271 control:control1|comb~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.386 ns) 8.060 ns control:control1\|en1 4 COMB LOOP LC_X20_Y6_N9 14 " "Info: 4: + IC(0.000 ns) + CELL(1.386 ns) = 8.060 ns; Loc. = LC_X20_Y6_N9; Fanout = 14; COMB LOOP Node = 'control:control1\|en1'" { { "Info" "ITDB_PART_OF_SCC" "control:control1\|en1 LC_X20_Y6_N9 " "Info: Loc. = LC_X20_Y6_N9; Node \"control:control1\|en1\"" {  } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { control:control1|en1 } "NODE_NAME" } "" } }  } 0}  } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { control:control1|en1 } "NODE_NAME" } "" } } { "control.v" "" { Text "F:/my_design/hdlc/control.v" 3 -1 0 } } { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "1.386 ns" { control:control1|comb~0 control:control1|en1 } "NODE_NAME" } "" } } { "control.v" "" { Text "F:/my_design/hdlc/control.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.686 ns) + CELL(1.622 ns) 11.368 ns en1 5 PIN PIN_40 0 " "Info: 5: + IC(1.686 ns) + CELL(1.622 ns) = 11.368 ns; Loc. = PIN_40; Fanout = 0; PIN Node = 'en1'" {  } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "3.308 ns" { control:control1|en1 en1 } "NODE_NAME" } "" } } { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.051 ns 44.43 % " "Info: Total cell delay = 5.051 ns ( 44.43 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.317 ns 55.57 % " "Info: Total interconnect delay = 6.317 ns ( 55.57 % )" {  } {  } 0}  } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "11.368 ns" { ept control:control1|always0~271 control:control1|comb~0 control:control1|en1 en1 } "NODE_NAME" } "" } } { "e:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/bin/Technology_Viewer.qrui" "11.368 ns" { ept ept~out0 control:control1|always0~271 control:control1|comb~0 control:control1|en1 en1 } { 0.000ns 0.000ns 4.295ns 0.336ns 0.000ns 1.686ns } { 0.000ns 1.135ns 0.454ns 0.454ns 1.386ns 1.622ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "control:control1\|reset2 ept clk -3.755 ns register " "Info: th for register \"control:control1\|reset2\" (data pin = \"ept\", clock pin = \"clk\") is -3.755 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.138 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.138 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 62 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 62; CLK Node = 'clk'" {  } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { clk } "NODE_NAME" } "" } } { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.461 ns) + CELL(0.547 ns) 2.138 ns control:control1\|reset2 2 REG LC_X19_Y7_N3 5 " "Info: 2: + IC(0.461 ns) + CELL(0.547 ns) = 2.138 ns; Loc. = LC_X19_Y7_N3; Fanout = 5; REG Node = 'control:control1\|reset2'" {  } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "1.008 ns" { clk control:control1|reset2 } "NODE_NAME" } "" } } { "control.v" "" { Text "F:/my_design/hdlc/control.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 78.44 % " "Info: Total cell delay = 1.677 ns ( 78.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.461 ns 21.56 % " "Info: Total interconnect delay = 0.461 ns ( 21.56 % )" {  } {  } 0}  } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "2.138 ns" { clk control:control1|reset2 } "NODE_NAME" } "" } } { "e:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/bin/Technology_Viewer.qrui" "2.138 ns" { clk clk~out0 control:control1|reset2 } { 0.000ns 0.000ns 0.461ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.012 ns + " "Info: + Micro hold delay of destination is 0.012 ns" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 4 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.905 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.905 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns ept 1 PIN PIN_41 9 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_41; Fanout = 9; PIN Node = 'ept'" {  } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { ept } "NODE_NAME" } "" } } { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.202 ns) + CELL(0.568 ns) 5.905 ns control:control1\|reset2 2 REG LC_X19_Y7_N3 5 " "Info: 2: + IC(4.202 ns) + CELL(0.568 ns) = 5.905 ns; Loc. = LC_X19_Y7_N3; Fanout = 5; REG Node = 'control:control1\|reset2'" {  } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "4.770 ns" { ept control:control1|reset2 } "NODE_NAME" } "" } } { "control.v" "" { Text "F:/my_design/hdlc/control.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.703 ns 28.84 % " "Info: Total cell delay = 1.703 ns ( 28.84 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.202 ns 71.16 % " "Info: Total interconnect delay = 4.202 ns ( 71.16 % )" {  } {  } 0}  } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "5.905 ns" { ept control:control1|reset2 } "NODE_NAME" } "" } } { "e:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/bin/Technology_Viewer.qrui" "5.905 ns" { ept ept~out0 control:control1|reset2 } { 0.000ns 0.000ns 4.202ns } { 0.000ns 1.135ns 0.568ns } } }  } 0}  } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "2.138 ns" { clk control:control1|reset2 } "NODE_NAME" } "" } } { "e:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/bin/Technology_Viewer.qrui" "2.138 ns" { clk clk~out0 control:control1|reset2 } { 0.000ns 0.000ns 0.461ns } { 0.000ns 1.130ns 0.547ns } } } { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "5.905 ns" { ept control:control1|reset2 } "NODE_NAME" } "" } } { "e:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/bin/Technology_Viewer.qrui" "5.905 ns" { ept ept~out0 control:control1|reset2 } { 0.000ns 0.000ns 4.202ns } { 0.000ns 1.135ns 0.568ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 4 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jul 01 22:51:53 2007 " "Info: Processing ended: Sun Jul 01 22:51:53 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}