📄 hdlc.tan.qmsg
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{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "control:control1\|en3 " "Info: Node \"control:control1\|en3\"" { } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 3 -1 0 } } } 0} } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 3 -1 0 } } } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 13 -1 0 } } { "e:/altera/bin/Assignment Editor.qase" "" { Assignment "e:/altera/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register control:control1\|count1\[1\] register shift32:shift\|crcout 138.72 MHz 7.209 ns Internal " "Info: Clock \"clk\" has Internal fmax of 138.72 MHz between source register \"control:control1\|count1\[1\]\" and destination register \"shift32:shift\|crcout\" (period= 7.209 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.979 ns + Longest register register " "Info: + Longest register to register delay is 6.979 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns control:control1\|count1\[1\] 1 REG LC_X20_Y6_N0 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y6_N0; Fanout = 7; REG Node = 'control:control1\|count1\[1\]'" { } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { control:control1|count1[1] } "NODE_NAME" } "" } } { "control.v" "" { Text "F:/my_design/hdlc/control.v" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.003 ns) + CELL(0.454 ns) 1.457 ns control:control1\|always0~267 2 COMB LC_X20_Y7_N2 1 " "Info: 2: + IC(1.003 ns) + CELL(0.454 ns) = 1.457 ns; Loc. = LC_X20_Y7_N2; Fanout = 1; COMB Node = 'control:control1\|always0~267'" { } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "1.457 ns" { control:control1|count1[1] control:control1|always0~267 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.140 ns) + CELL(0.088 ns) 1.685 ns control:control1\|always0~268 3 COMB LC_X20_Y7_N3 4 " "Info: 3: + IC(0.140 ns) + CELL(0.088 ns) = 1.685 ns; Loc. = LC_X20_Y7_N3; Fanout = 4; COMB Node = 'control:control1\|always0~268'" { } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "0.228 ns" { control:control1|always0~267 control:control1|always0~268 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.335 ns) + CELL(0.088 ns) 2.108 ns control:control1\|always0~11 4 COMB LC_X20_Y7_N0 4 " "Info: 4: + IC(0.335 ns) + CELL(0.088 ns) = 2.108 ns; Loc. = LC_X20_Y7_N0; Fanout = 4; COMB Node = 'control:control1\|always0~11'" { } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "0.423 ns" { control:control1|always0~268 control:control1|always0~11 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.562 ns) + CELL(0.225 ns) 2.895 ns control:control1\|comb~0 5 COMB LC_X20_Y7_N4 2 " "Info: 5: + IC(0.562 ns) + CELL(0.225 ns) = 2.895 ns; Loc. = LC_X20_Y7_N4; Fanout = 2; COMB Node = 'control:control1\|comb~0'" { } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "0.787 ns" { control:control1|always0~11 control:control1|comb~0 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.386 ns) 4.281 ns control:control1\|en1 6 COMB LOOP LC_X20_Y6_N9 14 " "Info: 6: + IC(0.000 ns) + CELL(1.386 ns) = 4.281 ns; Loc. = LC_X20_Y6_N9; Fanout = 14; COMB LOOP Node = 'control:control1\|en1'" { { "Info" "ITDB_PART_OF_SCC" "control:control1\|en1 LC_X20_Y6_N9 " "Info: Loc. = LC_X20_Y6_N9; Node \"control:control1\|en1\"" { } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { control:control1|en1 } "NODE_NAME" } "" } } } 0} } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { control:control1|en1 } "NODE_NAME" } "" } } { "control.v" "" { Text "F:/my_design/hdlc/control.v" 3 -1 0 } } { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "1.386 ns" { control:control1|comb~0 control:control1|en1 } "NODE_NAME" } "" } } { "control.v" "" { Text "F:/my_design/hdlc/control.v" 3 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.376 ns) + CELL(0.454 ns) 5.111 ns shift32:shift\|crcout~2 7 COMB LC_X20_Y6_N7 2 " "Info: 7: + IC(0.376 ns) + CELL(0.454 ns) = 5.111 ns; Loc. = LC_X20_Y6_N7; Fanout = 2; COMB Node = 'shift32:shift\|crcout~2'" { } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "0.830 ns" { control:control1|en1 shift32:shift|crcout~2 } "NODE_NAME" } "" } } { "shift32.v" "" { Text "F:/my_design/hdlc/shift32.v" 4 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.201 ns) + CELL(0.667 ns) 6.979 ns shift32:shift\|crcout 8 REG LC_X19_Y5_N8 9 " "Info: 8: + IC(1.201 ns) + CELL(0.667 ns) = 6.979 ns; Loc. = LC_X19_Y5_N8; Fanout = 9; REG Node = 'shift32:shift\|crcout'" { } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "1.868 ns" { shift32:shift|crcout~2 shift32:shift|crcout } "NODE_NAME" } "" } } { "shift32.v" "" { Text "F:/my_design/hdlc/shift32.v" 4 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.362 ns 48.17 % " "Info: Total cell delay = 3.362 ns ( 48.17 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.617 ns 51.83 % " "Info: Total interconnect delay = 3.617 ns ( 51.83 % )" { } { } 0} } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "6.979 ns" { control:control1|count1[1] control:control1|always0~267 control:control1|always0~268 control:control1|always0~11 control:control1|comb~0 control:control1|en1 shift32:shift|crcout~2 shift32:shift|crcout } "NODE_NAME" } "" } } { "e:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/bin/Technology_Viewer.qrui" "6.979 ns" { control:control1|count1[1] control:control1|always0~267 control:control1|always0~268 control:control1|always0~11 control:control1|comb~0 control:control1|en1 shift32:shift|crcout~2 shift32:shift|crcout } { 0.000ns 1.003ns 0.140ns 0.335ns 0.562ns 0.000ns 0.376ns 1.201ns } { 0.000ns 0.454ns 0.088ns 0.088ns 0.225ns 1.386ns 0.454ns 0.667ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.028 ns - Smallest " "Info: - Smallest clock skew is -0.028 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.110 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.110 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 62 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 62; CLK Node = 'clk'" { } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { clk } "NODE_NAME" } "" } } { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 13 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.433 ns) + CELL(0.547 ns) 2.110 ns shift32:shift\|crcout 2 REG LC_X19_Y5_N8 9 " "Info: 2: + IC(0.433 ns) + CELL(0.547 ns) = 2.110 ns; Loc. = LC_X19_Y5_N8; Fanout = 9; REG Node = 'shift32:shift\|crcout'" { } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "0.980 ns" { clk shift32:shift|crcout } "NODE_NAME" } "" } } { "shift32.v" "" { Text "F:/my_design/hdlc/shift32.v" 4 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 79.48 % " "Info: Total cell delay = 1.677 ns ( 79.48 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.433 ns 20.52 % " "Info: Total interconnect delay = 0.433 ns ( 20.52 % )" { } { } 0} } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "2.110 ns" { clk shift32:shift|crcout } "NODE_NAME" } "" } } { "e:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/bin/Technology_Viewer.qrui" "2.110 ns" { clk clk~out0 shift32:shift|crcout } { 0.000ns 0.000ns 0.433ns } { 0.000ns 1.130ns 0.547ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.138 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.138 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 62 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 62; CLK Node = 'clk'" { } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { clk } "NODE_NAME" } "" } } { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 13 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.461 ns) + CELL(0.547 ns) 2.138 ns control:control1\|count1\[1\] 2 REG LC_X20_Y6_N0 7 " "Info: 2: + IC(0.461 ns) + CELL(0.547 ns) = 2.138 ns; Loc. = LC_X20_Y6_N0; Fanout = 7; REG Node = 'control:control1\|count1\[1\]'" { } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "1.008 ns" { clk control:control1|count1[1] } "NODE_NAME" } "" } } { "control.v" "" { Text "F:/my_design/hdlc/control.v" 5 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 78.44 % " "Info: Total cell delay = 1.677 ns ( 78.44 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.461 ns 21.56 % " "Info: Total interconnect delay = 0.461 ns ( 21.56 % )" { } { } 0} } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "2.138 ns" { clk control:control1|count1[1] } "NODE_NAME" } "" } } { "e:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/bin/Technology_Viewer.qrui" "2.138 ns" { clk clk~out0 control:control1|count1[1] } { 0.000ns 0.000ns 0.461ns } { 0.000ns 1.130ns 0.547ns } } } } 0} } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "2.110 ns" { clk shift32:shift|crcout } "NODE_NAME" } "" } } { "e:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/bin/Technology_Viewer.qrui" "2.110 ns" { clk clk~out0 shift32:shift|crcout } { 0.000ns 0.000ns 0.433ns } { 0.000ns 1.130ns 0.547ns } } } { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "2.138 ns" { clk control:control1|count1[1] } "NODE_NAME" } "" } } { "e:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/bin/Technology_Viewer.qrui" "2.138 ns" { clk clk~out0 control:control1|count1[1] } { 0.000ns 0.000ns 0.461ns } { 0.000ns 1.130ns 0.547ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" { } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 5 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" { } { { "shift32.v" "" { Text "F:/my_design/hdlc/shift32.v" 4 -1 0 } } } 0} } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "6.979 ns" { control:control1|count1[1] control:control1|always0~267 control:control1|always0~268 control:control1|always0~11 control:control1|comb~0 control:control1|en1 shift32:shift|crcout~2 shift32:shift|crcout } "NODE_NAME" } "" } } { "e:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/bin/Technology_Viewer.qrui" "6.979 ns" { control:control1|count1[1] control:control1|always0~267 control:control1|always0~268 control:control1|always0~11 control:control1|comb~0 control:control1|en1 shift32:shift|crcout~2 shift32:shift|crcout } { 0.000ns 1.003ns 0.140ns 0.335ns 0.562ns 0.000ns 0.376ns 1.201ns } { 0.000ns 0.454ns 0.088ns 0.088ns 0.225ns 1.386ns 0.454ns 0.667ns } } } { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "2.110 ns" { clk shift32:shift|crcout } "NODE_NAME" } "" } } { "e:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/bin/Technology_Viewer.qrui" "2.110 ns" { clk clk~out0 shift32:shift|crcout } { 0.000ns 0.000ns 0.433ns } { 0.000ns 1.130ns 0.547ns } } } { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "2.138 ns" { clk control:control1|count1[1] } "NODE_NAME" } "" } } { "e:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/bin/Technology_Viewer.qrui" "2.138 ns" { clk clk~out0 control:control1|count1[1] } { 0.000ns 0.000ns 0.461ns } { 0.000ns 1.130ns 0.547ns } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "shift32:shift\|crcout ept clk 8.677 ns register " "Info: tsu for register \"shift32:shift\|crcout\" (data pin = \"ept\", clock pin = \"clk\") is 8.677 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.758 ns + Longest pin register " "Info: + Longest pin to register delay is 10.758 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns ept 1 PIN PIN_41 9 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_41; Fanout = 9; PIN Node = 'ept'" { } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { ept } "NODE_NAME" } "" } } { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 13 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.295 ns) + CELL(0.454 ns) 5.884 ns control:control1\|always0~271 2 COMB LC_X20_Y7_N6 2 " "Info: 2: + IC(4.295 ns) + CELL(0.454 ns) = 5.884 ns; Loc. = LC_X20_Y7_N6; Fanout = 2; COMB Node = 'control:control1\|always0~271'" { } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "4.749 ns" { ept control:control1|always0~271 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.336 ns) + CELL(0.454 ns) 6.674 ns control:control1\|comb~0 3 COMB LC_X20_Y7_N4 2 " "Info: 3: + IC(0.336 ns) + CELL(0.454 ns) = 6.674 ns; Loc. = LC_X20_Y7_N4; Fanout = 2; COMB Node = 'control:control1\|comb~0'" { } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "0.790 ns" { control:control1|always0~271 control:control1|comb~0 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.386 ns) 8.060 ns control:control1\|en1 4 COMB LOOP LC_X20_Y6_N9 14 " "Info: 4: + IC(0.000 ns) + CELL(1.386 ns) = 8.060 ns; Loc. = LC_X20_Y6_N9; Fanout = 14; COMB LOOP Node = 'control:control1\|en1'" { { "Info" "ITDB_PART_OF_SCC" "control:control1\|en1 LC_X20_Y6_N9 " "Info: Loc. = LC_X20_Y6_N9; Node \"control:control1\|en1\"" { } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { control:control1|en1 } "NODE_NAME" } "" } } } 0} } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { control:control1|en1 } "NODE_NAME" } "" } } { "control.v" "" { Text "F:/my_design/hdlc/control.v" 3 -1 0 } } { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "1.386 ns" { control:control1|comb~0 control:control1|en1 } "NODE_NAME" } "" } } { "control.v" "" { Text "F:/my_design/hdlc/control.v" 3 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.376 ns) + CELL(0.454 ns) 8.890 ns shift32:shift\|crcout~2 5 COMB LC_X20_Y6_N7 2 " "Info: 5: + IC(0.376 ns) + CELL(0.454 ns) = 8.890 ns; Loc. = LC_X20_Y6_N7; Fanout = 2; COMB Node = 'shift32:shift\|crcout~2'" { } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "0.830 ns" { control:control1|en1 shift32:shift|crcout~2 } "NODE_NAME" } "" } } { "shift32.v" "" { Text "F:/my_design/hdlc/shift32.v" 4 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.201 ns) + CELL(0.667 ns) 10.758 ns shift32:shift\|crcout 6 REG LC_X19_Y5_N8 9 " "Info: 6: + IC(1.201 ns) + CELL(0.667 ns) = 10.758 ns; Loc. = LC_X19_Y5_N8; Fanout = 9; REG Node = 'shift32:shift\|crcout'" { } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "1.868 ns" { shift32:shift|crcout~2 shift32:shift|crcout } "NODE_NAME" } "" } } { "shift32.v" "" { Text "F:/my_design/hdlc/shift32.v" 4 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.550 ns 42.29 % " "Info: Total cell delay = 4.550 ns ( 42.29 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.208 ns 57.71 % " "Info: Total interconnect delay = 6.208 ns ( 57.71 % )" { } { } 0} } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "10.758 ns" { ept control:control1|always0~271 control:control1|comb~0 control:control1|en1 shift32:shift|crcout~2 shift32:shift|crcout } "NODE_NAME" } "" } } { "e:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/bin/Technology_Viewer.qrui" "10.758 ns" { ept ept~out0 control:control1|always0~271 control:control1|comb~0 control:control1|en1 shift32:shift|crcout~2 shift32:shift|crcout } { 0.000ns 0.000ns 4.295ns 0.336ns 0.000ns 0.376ns 1.201ns } { 0.000ns 1.135ns 0.454ns 0.454ns 1.386ns 0.454ns 0.667ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" { } { { "shift32.v" "" { Text "F:/my_design/hdlc/shift32.v" 4 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.110 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.110 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 62 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 62; CLK Node = 'clk'" { } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { clk } "NODE_NAME" } "" } } { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 13 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.433 ns) + CELL(0.547 ns) 2.110 ns shift32:shift\|crcout 2 REG LC_X19_Y5_N8 9 " "Info: 2: + IC(0.433 ns) + CELL(0.547 ns) = 2.110 ns; Loc. = LC_X19_Y5_N8; Fanout = 9; REG Node = 'shift32:shift\|crcout'" { } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "0.980 ns" { clk shift32:shift|crcout } "NODE_NAME" } "" } } { "shift32.v" "" { Text "F:/my_design/hdlc/shift32.v" 4 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 79.48 % " "Info: Total cell delay = 1.677 ns ( 79.48 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.433 ns 20.52 % " "Info: Total interconnect delay = 0.433 ns ( 20.52 % )" { } { } 0} } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "2.110 ns" { clk shift32:shift|crcout } "NODE_NAME" } "" } } { "e:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/bin/Technology_Viewer.qrui" "2.110 ns" { clk clk~out0 shift32:shift|crcout } { 0.000ns 0.000ns 0.433ns } { 0.000ns 1.130ns 0.547ns } } } } 0} } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "10.758 ns" { ept control:control1|always0~271 control:control1|comb~0 control:control1|en1 shift32:shift|crcout~2 shift32:shift|crcout } "NODE_NAME" } "" } } { "e:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/bin/Technology_Viewer.qrui" "10.758 ns" { ept ept~out0 control:control1|always0~271 control:control1|comb~0 control:control1|en1 shift32:shift|crcout~2 shift32:shift|crcout } { 0.000ns 0.000ns 4.295ns 0.336ns 0.000ns 0.376ns 1.201ns } { 0.000ns 1.135ns 0.454ns 0.454ns 1.386ns 0.454ns 0.667ns } } } { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "2.110 ns" { clk shift32:shift|crcout } "NODE_NAME" } "" } } { "e:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/bin/Technology_Viewer.qrui" "2.110 ns" { clk clk~out0 shift32:shift|crcout } { 0.000ns 0.000ns 0.433ns } { 0.000ns 1.130ns 0.547ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk en1 control:control1\|count1\[1\] 9.900 ns register " "Info: tco from clock \"clk\" to destination pin \"en1\" through register \"control:control1\|count1\[1\]\" is 9.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.138 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.138 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 62 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 62; CLK Node = 'clk'" { } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { clk } "NODE_NAME" } "" } } { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 13 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.461 ns) + CELL(0.547 ns) 2.138 ns control:control1\|count1\[1\] 2 REG LC_X20_Y6_N0 7 " "Info: 2: + IC(0.461 ns) + CELL(0.547 ns) = 2.138 ns; Loc. = LC_X20_Y6_N0; Fanout = 7; REG Node = 'control:control1\|count1\[1\]'" { } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "1.008 ns" { clk control:control1|count1[1] } "NODE_NAME" } "" } } { "control.v" "" { Text "F:/my_design/hdlc/control.v" 5 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 78.44 % " "Info: Total cell delay = 1.677 ns ( 78.44 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.461 ns 21.56 % " "Info: Total interconnect delay = 0.461 ns ( 21.56 % )" { } { } 0} } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "2.138 ns" { clk control:control1|count1[1] } "NODE_NAME" } "" } } { "e:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/bin/Technology_Viewer.qrui" "2.138 ns" { clk clk~out0 control:control1|count1[1] } { 0.000ns 0.000ns 0.461ns } { 0.000ns 1.130ns 0.547ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" { } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 5 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.589 ns + Longest register pin " "Info: + Longest register to pin delay is 7.589 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns control:control1\|count1\[1\] 1 REG LC_X20_Y6_N0 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y6_N0; Fanout = 7; REG Node = 'control:control1\|count1\[1\]'" { } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { control:control1|count1[1] } "NODE_NAME" } "" } } { "control.v" "" { Text "F:/my_design/hdlc/control.v" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.003 ns) + CELL(0.454 ns) 1.457 ns control:control1\|always0~267 2 COMB LC_X20_Y7_N2 1 " "Info: 2: + IC(1.003 ns) + CELL(0.454 ns) = 1.457 ns; Loc. = LC_X20_Y7_N2; Fanout = 1; COMB Node = 'control:control1\|always0~267'" { } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "1.457 ns" { control:control1|count1[1] control:control1|always0~267 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.140 ns) + CELL(0.088 ns) 1.685 ns control:control1\|always0~268 3 COMB LC_X20_Y7_N3 4 " "Info: 3: + IC(0.140 ns) + CELL(0.088 ns) = 1.685 ns; Loc. = LC_X20_Y7_N3; Fanout = 4; COMB Node = 'control:control1\|always0~268'" { } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "0.228 ns" { control:control1|always0~267 control:control1|always0~268 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.335 ns) + CELL(0.088 ns) 2.108 ns control:control1\|always0~11 4 COMB LC_X20_Y7_N0 4 " "Info: 4: + IC(0.335 ns) + CELL(0.088 ns) = 2.108 ns; Loc. = LC_X20_Y7_N0; Fanout = 4; COMB Node = 'control:control1\|always0~11'" { } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "0.423 ns" { control:control1|always0~268 control:control1|always0~11 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.562 ns) + CELL(0.225 ns) 2.895 ns control:control1\|comb~0 5 COMB LC_X20_Y7_N4 2 " "Info: 5: + IC(0.562 ns) + CELL(0.225 ns) = 2.895 ns; Loc. = LC_X20_Y7_N4; Fanout = 2; COMB Node = 'control:control1\|comb~0'" { } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "0.787 ns" { control:control1|always0~11 control:control1|comb~0 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.386 ns) 4.281 ns control:control1\|en1 6 COMB LOOP LC_X20_Y6_N9 14 " "Info: 6: + IC(0.000 ns) + CELL(1.386 ns) = 4.281 ns; Loc. = LC_X20_Y6_N9; Fanout = 14; COMB LOOP Node = 'control:control1\|en1'" { { "Info" "ITDB_PART_OF_SCC" "control:control1\|en1 LC_X20_Y6_N9 " "Info: Loc. = LC_X20_Y6_N9; Node \"control:control1\|en1\"" { } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { control:control1|en1 } "NODE_NAME" } "" } } } 0} } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { control:control1|en1 } "NODE_NAME" } "" } } { "control.v" "" { Text "F:/my_design/hdlc/control.v" 3 -1 0 } } { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "1.386 ns" { control:control1|comb~0 control:control1|en1 } "NODE_NAME" } "" } } { "control.v" "" { Text "F:/my_design/hdlc/control.v" 3 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.686 ns) + CELL(1.622 ns) 7.589 ns en1 7 PIN PIN_40 0 " "Info: 7: + IC(1.686 ns) + CELL(1.622 ns) = 7.589 ns; Loc. = PIN_40; Fanout = 0; PIN Node = 'en1'" { } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "3.308 ns" { control:control1|en1 en1 } "NODE_NAME" } "" } } { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 14 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.863 ns 50.90 % " "Info: Total cell delay = 3.863 ns ( 50.90 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.726 ns 49.10 % " "Info: Total interconnect delay = 3.726 ns ( 49.10 % )" { } { } 0} } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "7.589 ns" { control:control1|count1[1] control:control1|always0~267 control:control1|always0~268 control:control1|always0~11 control:control1|comb~0 control:control1|en1 en1 } "NODE_NAME" } "" } } { "e:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/bin/Technology_Viewer.qrui" "7.589 ns" { control:control1|count1[1] control:control1|always0~267 control:control1|always0~268 control:control1|always0~11 control:control1|comb~0 control:control1|en1 en1 } { 0.000ns 1.003ns 0.140ns 0.335ns 0.562ns 0.000ns 1.686ns } { 0.000ns 0.454ns 0.088ns 0.088ns 0.225ns 1.386ns 1.622ns } } } } 0} } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "2.138 ns" { clk control:control1|count1[1] } "NODE_NAME" } "" } } { "e:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/bin/Technology_Viewer.qrui" "2.138 ns" { clk clk~out0 control:control1|count1[1] } { 0.000ns 0.000ns 0.461ns } { 0.000ns 1.130ns 0.547ns } } } { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "7.589 ns" { control:control1|count1[1] control:control1|always0~267 control:control1|always0~268 control:control1|always0~11 control:control1|comb~0 control:control1|en1 en1 } "NODE_NAME" } "" } } { "e:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/bin/Technology_Viewer.qrui" "7.589 ns" { control:control1|count1[1] control:control1|always0~267 control:control1|always0~268 control:control1|always0~11 control:control1|comb~0 control:control1|en1 en1 } { 0.000ns 1.003ns 0.140ns 0.335ns 0.562ns 0.000ns 1.686ns } { 0.000ns 0.454ns 0.088ns 0.088ns 0.225ns 1.386ns 1.622ns } } } } 0}
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