hdlc.tan.qmsg

该工程是基于verilog hdl 语言编写的帧传输协议HDLC帧的发送端代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jul 01 22:51:53 2007 " "Info: Processing started: Sun Jul 01 22:51:53 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off hdlc -c hdlc --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off hdlc -c hdlc --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_FOUND_COMB_LATCHES" "" "Warning: Timing Analysis found one or more latches implemented as combinational loops" { { "Warning" "WTAN_COMB_LATCH_NODE" "control:control1\|en3 " "Warning: Node \"control:control1\|en3\" is a latch" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 3 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "control:control1\|en1 " "Warning: Node \"control:control1\|en1\" is a latch" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "control:control1\|en1 " "Info: Node \"control:control1\|en1\"" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 3 -1 0 } }  } 0}  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 3 -1 0 } }  } 0}