hdlc.hier_info

该工程是基于verilog hdl 语言编写的帧传输协议HDLC帧的发送端代码

|hdlc
clk => clk~0.IN4
reset1 => reset1~0.IN2
ept => ept~0.IN2
dout <= mux3:mux.dout
dout1 <= shift32:shift.crcout
dout2 <= dout2~0.DB_MAX_OUTPUT_PORT_TYPE
dout3 <= dout3~0.DB_MAX_OUTPUT_PORT_TYPE
dout4 <= dout4~0.DB_MAX_OUTPUT_PORT_TYPE
din <= <GND>
flag <= flag~0.DB_MAX_OUTPUT_PORT_TYPE
en1 <= en1~0.DB_MAX_OUTPUT_PORT_TYPE
en2 <= en2~0.DB_MAX_OUTPUT_PORT_TYPE
en3 <= en3~0.DB_MAX_OUTPUT_PORT_TYPE
sel1 <= sel1~0.DB_MAX_OUTPUT_PORT_TYPE
sel2 <= sel2~0.DB_MAX_OUTPUT_PORT_TYPE
sel3 <= <GND>
clkout <= shift32:shift.clkout


|hdlc|shift32:shift
clk => flag~reg0.CLK
clk => count1[5].CLK
clk => count1[4].CLK
clk => count1[3].CLK
clk => count1[2].CLK
clk => count1[1].CLK
clk => count1[0].CLK
clk => crc_reg[15].CLK
clk => crc_reg[14].CLK
clk => crc_reg[13].CLK
clk => crc_reg[12].CLK
clk => crc_reg[11].CLK
clk => crc_reg[10].CLK
clk => crc_reg[9].CLK
clk => crc_reg[8].CLK
clk => crc_reg[7].CLK
clk => crc_reg[6].CLK
clk => crc_reg[5].CLK
clk => crc_reg[4].CLK
clk => crc_reg[3].CLK
clk => crc_reg[2].CLK
clk => crc_reg[1].CLK
clk => crc_reg[0].CLK
clk => count[5].CLK
clk => count[4].CLK
clk => count[3].CLK
clk => count[2].CLK
clk => count[1].CLK
clk => count[0].CLK
clk => dout.CLK
clk => crcout~reg0.CLK
clk => state~5.IN1
en1 => state~0.OUTPUTSELECT
en1 => state~1.OUTPUTSELECT
en1 => state~2.OUTPUTSELECT
en1 => state~3.OUTPUTSELECT
en1 => state~4.OUTPUTSELECT
en1 => always1~0.IN1
en1 => flag~reg0.ENA
sel1 => crcout~0.OUTPUTSELECT
sel1 => crc_reg~5.OUTPUTSELECT
sel1 => crc_reg~6.OUTPUTSELECT
sel1 => crc_reg~7.OUTPUTSELECT
sel1 => crc_reg~8.OUTPUTSELECT
sel1 => crc_reg~9.OUTPUTSELECT
sel1 => crc_reg~10.OUTPUTSELECT
sel1 => crc_reg~11.OUTPUTSELECT
sel1 => crc_reg~12.OUTPUTSELECT
sel1 => crc_reg~13.OUTPUTSELECT
sel1 => crc_reg~14.OUTPUTSELECT
sel1 => crc_reg~15.OUTPUTSELECT
sel1 => crc_reg~16.OUTPUTSELECT
sel1 => crc_reg~17.OUTPUTSELECT
sel1 => crc_reg~18.OUTPUTSELECT
sel1 => crc_reg~19.OUTPUTSELECT
sel1 => crc_reg~20.OUTPUTSELECT
sel1 => count~6.OUTPUTSELECT
sel1 => count~7.OUTPUTSELECT
sel1 => count~8.OUTPUTSELECT
sel1 => count~9.OUTPUTSELECT
sel1 => count~10.OUTPUTSELECT
sel1 => count~11.OUTPUTSELECT
reset => count1~6.OUTPUTSELECT
reset => count1~7.OUTPUTSELECT
reset => count1~8.OUTPUTSELECT
reset => count1~9.OUTPUTSELECT
reset => count1~10.OUTPUTSELECT
reset => count1~11.OUTPUTSELECT
reset => crc_reg~21.OUTPUTSELECT
reset => crc_reg~22.OUTPUTSELECT
reset => crc_reg~23.OUTPUTSELECT
reset => crc_reg~24.OUTPUTSELECT
reset => crc_reg~25.OUTPUTSELECT
reset => crc_reg~26.OUTPUTSELECT
reset => crc_reg~27.OUTPUTSELECT
reset => crc_reg~28.OUTPUTSELECT
reset => crc_reg~29.OUTPUTSELECT
reset => crc_reg~30.OUTPUTSELECT
reset => crc_reg~31.OUTPUTSELECT
reset => crc_reg~32.OUTPUTSELECT
reset => crc_reg~33.OUTPUTSELECT
reset => crc_reg~34.OUTPUTSELECT
reset => crc_reg~35.OUTPUTSELECT
reset => crc_reg~36.OUTPUTSELECT
reset => count~12.OUTPUTSELECT
reset => count~13.OUTPUTSELECT
reset => count~14.OUTPUTSELECT
reset => count~15.OUTPUTSELECT
reset => count~16.OUTPUTSELECT
reset => count~17.OUTPUTSELECT
crcout <= crcout~reg0.DB_MAX_OUTPUT_PORT_TYPE
clkout <= <GND>
flag <= flag~reg0.DB_MAX_OUTPUT_PORT_TYPE
out <= out~0.DB_MAX_OUTPUT_PORT_TYPE


|hdlc|flag1:flag11
en2 => count[2].ENA
en2 => count[1].ENA
en2 => count[0].ENA
en2 => dout~reg0.ENA
en2 => count[3].ENA
clk => count[2].CLK
clk => count[1].CLK
clk => count[0].CLK
clk => dout~reg0.CLK
clk => count[3].CLK
dout <= dout~reg0.DB_MAX_OUTPUT_PORT_TYPE


|hdlc|free:free1
clk => count[3].CLK
clk => count[2].CLK
clk => count[1].CLK
clk => count[0].CLK
clk => d[7].CLK
clk => d[6].CLK
clk => d[5].CLK
clk => d[4].CLK
clk => d[3].CLK
clk => d[2].CLK
clk => d[1].CLK
clk => d[0].CLK
clk => dout~reg0.CLK
en3 => count~8.OUTPUTSELECT
en3 => count~9.OUTPUTSELECT
en3 => count~10.OUTPUTSELECT
en3 => count~11.OUTPUTSELECT
en3 => d[7].ENA
en3 => d[6].ENA
en3 => d[5].ENA
en3 => d[4].ENA
en3 => d[3].ENA
en3 => d[2].ENA
en3 => d[1].ENA
en3 => d[0].ENA
en3 => dout~reg0.ENA
dout <= dout~reg0.DB_MAX_OUTPUT_PORT_TYPE


|hdlc|mux3:mux
flag => always0~4.DATAB
free => always0~2.DATAA
signo => always0~2.DATAB
ept => always0~1.IN1
ept => always0~0.IN1
sel2 => always0~0.IN0
sel2 => always0~1.IN0
sel2 => always0~4.OUTPUTSELECT
sel2 => always0~5.IN0
dout <= dout$latch.DB_MAX_OUTPUT_PORT_TYPE


|hdlc|control:control1
clk => sel2~reg0.CLK
clk => en2~reg0.CLK
clk => reset2.CLK
clk => count2[3].CLK
clk => count2[2].CLK
clk => count2[1].CLK
clk => count2[0].CLK
clk => rd~reg0.CLK
clk => count1[5].CLK
clk => count1[4].CLK
clk => count1[3].CLK
clk => count1[2].CLK
clk => count1[1].CLK
clk => count1[0].CLK
clk => count3[3].CLK
clk => count3[2].CLK
clk => count3[1].CLK
clk => count3[0].CLK
clk => sel1~reg0.CLK
ept => always0~5.IN0
ept => reset2~8.OUTPUTSELECT
ept => sel1~3.OUTPUTSELECT
ept => reset2~9.OUTPUTSELECT
ept => always0~4.IN0
ept => always0~3.IN0
rd <= rd~reg0.DB_MAX_OUTPUT_PORT_TYPE
reset1 => always1~0.IN1
flag => always0~0.IN1
flag => always0~2.IN1
en1 <= en1$latch.DB_MAX_OUTPUT_PORT_TYPE
en2 <= en2~reg0.DB_MAX_OUTPUT_PORT_TYPE
en3 <= en3$latch.DB_MAX_OUTPUT_PORT_TYPE
sel1 <= sel1~reg0.DB_MAX_OUTPUT_PORT_TYPE
sel2 <= sel2~reg0.DB_MAX_OUTPUT_PORT_TYPE