hdlc.fit.qmsg

该工程是基于verilog hdl 语言编写的帧传输协议HDLC帧的发送端代码

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "16 unused 3.30 2 14 0 " "Info: Number of I/O pins in group: 16 (unused VREF, 3.30 VCCIO, 2 input, 14 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 3 11 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  11 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 17 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 17 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 17 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.762 ns register register " "Info: Estimated most critical path is register to register delay of 5.762 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns control:control1\|count1\[1\] 1 REG LAB_X20_Y6 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X20_Y6; Fanout = 7; REG Node = 'control:control1\|count1\[1\]'" {  } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { control:control1|count1[1] } "NODE_NAME" } "" } } { "control.v" "" { Text "F:/my_design/hdlc/control.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.890 ns) + CELL(0.225 ns) 1.115 ns control:control1\|always0~267 2 COMB LAB_X20_Y7 1 " "Info: 2: + IC(0.890 ns) + CELL(0.225 ns) = 1.115 ns; Loc. = LAB_X20_Y7; Fanout = 1; COMB Node = 'control:control1\|always0~267'" {  } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "1.115 ns" { control:control1|count1[1] control:control1|always0~267 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.286 ns) + CELL(0.225 ns) 1.626 ns control:control1\|always0~268 3 COMB LAB_X20_Y7 4 " "Info: 3: + IC(0.286 ns) + CELL(0.225 ns) = 1.626 ns; Loc. = LAB_X20_Y7; Fanout = 4; COMB Node = 'control:control1\|always0~268'" {  } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "0.511 ns" { control:control1|always0~267 control:control1|always0~268 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.171 ns) + CELL(0.340 ns) 2.137 ns control:control1\|always0~11 4 COMB LAB_X20_Y7 4 " "Info: 4: + IC(0.171 ns) + CELL(0.340 ns) = 2.137 ns; Loc. = LAB_X20_Y7; Fanout = 4; COMB Node = 'control:control1\|always0~11'" {  } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "0.511 ns" { control:control1|always0~268 control:control1|always0~11 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.716 ns) + CELL(0.340 ns) 3.193 ns control:control1\|en1 5 COMB LAB_X20_Y6 14 " "Info: 5: + IC(0.716 ns) + CELL(0.340 ns) = 3.193 ns; Loc. = LAB_X20_Y6; Fanout = 14; COMB Node = 'control:control1\|en1'" {  } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "1.056 ns" { control:control1|always0~11 control:control1|en1 } "NODE_NAME" } "" } } { "control.v" "" { Text "F:/my_design/hdlc/control.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.057 ns) + CELL(0.454 ns) 3.704 ns control:control1\|count1\[5\]~336 6 COMB LAB_X20_Y6 2 " "Info: 6: + IC(0.057 ns) + CELL(0.454 ns) = 3.704 ns; Loc. = LAB_X20_Y6; Fanout = 2; COMB Node = 'control:control1\|count1\[5\]~336'" {  } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "0.511 ns" { control:control1|en1 control:control1|count1[5]~336 } "NODE_NAME" } "" } } { "control.v" "" { Text "F:/my_design/hdlc/control.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.057 ns) + CELL(0.454 ns) 4.215 ns control:control1\|count1\[5\]~337 7 COMB LAB_X20_Y6 6 " "Info: 7: + IC(0.057 ns) + CELL(0.454 ns) = 4.215 ns; Loc. = LAB_X20_Y6; Fanout = 6; COMB Node = 'control:control1\|count1\[5\]~337'" {  } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "0.511 ns" { control:control1|count1[5]~336 control:control1|count1[5]~337 } "NODE_NAME" } "" } } { "control.v" "" { Text "F:/my_design/hdlc/control.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.880 ns) + CELL(0.667 ns) 5.762 ns control:control1\|count1\[3\] 8 REG LAB_X20_Y7 3 " "Info: 8: + IC(0.880 ns) + CELL(0.667 ns) = 5.762 ns; Loc. = LAB_X20_Y7; Fanout = 3; REG Node = 'control:control1\|count1\[3\]'" {  } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "1.547 ns" { control:control1|count1[5]~337 control:control1|count1[3] } "NODE_NAME" } "" } } { "control.v" "" { Text "F:/my_design/hdlc/control.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.705 ns 46.95 % " "Info: Total cell delay = 2.705 ns ( 46.95 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.057 ns 53.05 % " "Info: Total interconnect delay = 3.057 ns ( 53.05 % )" {  } {  } 0}  } { { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "5.762 ns" { control:control1|count1[1] control:control1|always0~267 control:control1|always0~268 control:control1|always0~11 control:control1|en1 control:control1|count1[5]~336 control:control1|count1[5]~337 control:control1|count1[3] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "3 " "Warning: The following 3 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "din GND " "Info: Pin din has GND driving its datain port" {  } { { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 14 -1 0 } } { "e:/altera/bin/Assignment Editor.qase" "" { Assignment "e:/altera/bin/Assignment Editor.qase" 1 { { 0 "din" } } } } { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { din } "NODE_NAME" } "" } } { "F:/my_design/hdlc/hdlc.fld" "" { Floorplan "F:/my_design/hdlc/hdlc.fld" "" "" { din } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "sel3 GND " "Info: Pin sel3 has GND driving its datain port" {  } { { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 15 -1 0 } } { "e:/altera/bin/Assignment Editor.qase" "" { Assignment "e:/altera/bin/Assignment Editor.qase" 1 { { 0 "sel3" } } } } { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { sel3 } "NODE_NAME" } "" } } { "F:/my_design/hdlc/hdlc.fld" "" { Floorplan "F:/my_design/hdlc/hdlc.fld" "" "" { sel3 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "clkout GND " "Info: Pin clkout has GND driving its datain port" {  } { { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 14 -1 0 } } { "e:/altera/bin/Assignment Editor.qase" "" { Assignment "e:/altera/bin/Assignment Editor.qase" 1 { { 0 "clkout" } } } } { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { clkout } "NODE_NAME" } "" } } { "F:/my_design/hdlc/hdlc.fld" "" { Floorplan "F:/my_design/hdlc/hdlc.fld" "" "" { clkout } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jul 01 22:51:48 2007 " "Info: Processing ended: Sun Jul 01 22:51:48 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}