hdlc.fit.qmsg

该工程是基于verilog hdl 语言编写的帧传输协议HDLC帧的发送端代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jul 01 22:51:44 2007 " "Info: Processing started: Sun Jul 01 22:51:44 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off hdlc -c hdlc " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off hdlc -c hdlc" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "hdlc EP1C3T100C6 " "Info: Selected device EP1C3T100C6 for design \"hdlc\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " {  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "17 17 " "Info: No exact pin location assignment(s) for 17 pins of 17 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "dout " "Info: Pin dout not assigned to an exact location on the device" {  } { { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 14 -1 0 } } { "e:/altera/bin/Assignment Editor.qase" "" { Assignment "e:/altera/bin/Assignment Editor.qase" 1 { { 0 "dout" } } } } { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { dout } "NODE_NAME" } "" } } { "F:/my_design/hdlc/hdlc.fld" "" { Floorplan "F:/my_design/hdlc/hdlc.fld" "" "" { dout } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "dout1 " "Info: Pin dout1 not assigned to an exact location on the device" {  } { { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 14 -1 0 } } { "e:/altera/bin/Assignment Editor.qase" "" { Assignment "e:/altera/bin/Assignment Editor.qase" 1 { { 0 "dout1" } } } } { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { dout1 } "NODE_NAME" } "" } } { "F:/my_design/hdlc/hdlc.fld" "" { Floorplan "F:/my_design/hdlc/hdlc.fld" "" "" { dout1 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "dout2 " "Info: Pin dout2 not assigned to an exact location on the device" {  } { { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 14 -1 0 } } { "e:/altera/bin/Assignment Editor.qase" "" { Assignment "e:/altera/bin/Assignment Editor.qase" 1 { { 0 "dout2" } } } } { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { dout2 } "NODE_NAME" } "" } } { "F:/my_design/hdlc/hdlc.fld" "" { Floorplan "F:/my_design/hdlc/hdlc.fld" "" "" { dout2 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "dout3 " "Info: Pin dout3 not assigned to an exact location on the device" {  } { { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 14 -1 0 } } { "e:/altera/bin/Assignment Editor.qase" "" { Assignment "e:/altera/bin/Assignment Editor.qase" 1 { { 0 "dout3" } } } } { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { dout3 } "NODE_NAME" } "" } } { "F:/my_design/hdlc/hdlc.fld" "" { Floorplan "F:/my_design/hdlc/hdlc.fld" "" "" { dout3 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "dout4 " "Info: Pin dout4 not assigned to an exact location on the device" {  } { { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 14 -1 0 } } { "e:/altera/bin/Assignment Editor.qase" "" { Assignment "e:/altera/bin/Assignment Editor.qase" 1 { { 0 "dout4" } } } } { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { dout4 } "NODE_NAME" } "" } } { "F:/my_design/hdlc/hdlc.fld" "" { Floorplan "F:/my_design/hdlc/hdlc.fld" "" "" { dout4 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "din " "Info: Pin din not assigned to an exact location on the device" {  } { { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 14 -1 0 } } { "e:/altera/bin/Assignment Editor.qase" "" { Assignment "e:/altera/bin/Assignment Editor.qase" 1 { { 0 "din" } } } } { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { din } "NODE_NAME" } "" } } { "F:/my_design/hdlc/hdlc.fld" "" { Floorplan "F:/my_design/hdlc/hdlc.fld" "" "" { din } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "flag " "Info: Pin flag not assigned to an exact location on the device" {  } { { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 14 -1 0 } } { "e:/altera/bin/Assignment Editor.qase" "" { Assignment "e:/altera/bin/Assignment Editor.qase" 1 { { 0 "flag" } } } } { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { flag } "NODE_NAME" } "" } } { "F:/my_design/hdlc/hdlc.fld" "" { Floorplan "F:/my_design/hdlc/hdlc.fld" "" "" { flag } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "en1 " "Info: Pin en1 not assigned to an exact location on the device" {  } { { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 14 -1 0 } } { "e:/altera/bin/Assignment Editor.qase" "" { Assignment "e:/altera/bin/Assignment Editor.qase" 1 { { 0 "en1" } } } } { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { en1 } "NODE_NAME" } "" } } { "F:/my_design/hdlc/hdlc.fld" "" { Floorplan "F:/my_design/hdlc/hdlc.fld" "" "" { en1 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "en2 " "Info: Pin en2 not assigned to an exact location on the device" {  } { { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 14 -1 0 } } { "e:/altera/bin/Assignment Editor.qase" "" { Assignment "e:/altera/bin/Assignment Editor.qase" 1 { { 0 "en2" } } } } { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { en2 } "NODE_NAME" } "" } } { "F:/my_design/hdlc/hdlc.fld" "" { Floorplan "F:/my_design/hdlc/hdlc.fld" "" "" { en2 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "en3 " "Info: Pin en3 not assigned to an exact location on the device" {  } { { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 14 -1 0 } } { "e:/altera/bin/Assignment Editor.qase" "" { Assignment "e:/altera/bin/Assignment Editor.qase" 1 { { 0 "en3" } } } } { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { en3 } "NODE_NAME" } "" } } { "F:/my_design/hdlc/hdlc.fld" "" { Floorplan "F:/my_design/hdlc/hdlc.fld" "" "" { en3 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "sel1 " "Info: Pin sel1 not assigned to an exact location on the device" {  } { { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 15 -1 0 } } { "e:/altera/bin/Assignment Editor.qase" "" { Assignment "e:/altera/bin/Assignment Editor.qase" 1 { { 0 "sel1" } } } } { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { sel1 } "NODE_NAME" } "" } } { "F:/my_design/hdlc/hdlc.fld" "" { Floorplan "F:/my_design/hdlc/hdlc.fld" "" "" { sel1 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "sel2 " "Info: Pin sel2 not assigned to an exact location on the device" {  } { { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 15 -1 0 } } { "e:/altera/bin/Assignment Editor.qase" "" { Assignment "e:/altera/bin/Assignment Editor.qase" 1 { { 0 "sel2" } } } } { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { sel2 } "NODE_NAME" } "" } } { "F:/my_design/hdlc/hdlc.fld" "" { Floorplan "F:/my_design/hdlc/hdlc.fld" "" "" { sel2 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "sel3 " "Info: Pin sel3 not assigned to an exact location on the device" {  } { { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 15 -1 0 } } { "e:/altera/bin/Assignment Editor.qase" "" { Assignment "e:/altera/bin/Assignment Editor.qase" 1 { { 0 "sel3" } } } } { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { sel3 } "NODE_NAME" } "" } } { "F:/my_design/hdlc/hdlc.fld" "" { Floorplan "F:/my_design/hdlc/hdlc.fld" "" "" { sel3 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "clkout " "Info: Pin clkout not assigned to an exact location on the device" {  } { { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 14 -1 0 } } { "e:/altera/bin/Assignment Editor.qase" "" { Assignment "e:/altera/bin/Assignment Editor.qase" 1 { { 0 "clkout" } } } } { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { clkout } "NODE_NAME" } "" } } { "F:/my_design/hdlc/hdlc.fld" "" { Floorplan "F:/my_design/hdlc/hdlc.fld" "" "" { clkout } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "ept " "Info: Pin ept not assigned to an exact location on the device" {  } { { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 13 -1 0 } } { "e:/altera/bin/Assignment Editor.qase" "" { Assignment "e:/altera/bin/Assignment Editor.qase" 1 { { 0 "ept" } } } } { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { ept } "NODE_NAME" } "" } } { "F:/my_design/hdlc/hdlc.fld" "" { Floorplan "F:/my_design/hdlc/hdlc.fld" "" "" { ept } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "clk " "Info: Pin clk not assigned to an exact location on the device" {  } { { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 13 -1 0 } } { "e:/altera/bin/Assignment Editor.qase" "" { Assignment "e:/altera/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { clk } "NODE_NAME" } "" } } { "F:/my_design/hdlc/hdlc.fld" "" { Floorplan "F:/my_design/hdlc/hdlc.fld" "" "" { clk } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "reset1 " "Info: Pin reset1 not assigned to an exact location on the device" {  } { { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 13 -1 0 } } { "e:/altera/bin/Assignment Editor.qase" "" { Assignment "e:/altera/bin/Assignment Editor.qase" 1 { { 0 "reset1" } } } } { "F:/my_design/hdlc/db/hdlc_cmp.qrpt" "" { Report "F:/my_design/hdlc/db/hdlc_cmp.qrpt" Compiler "hdlc" "UNKNOWN" "V1" "F:/my_design/hdlc/db/hdlc.quartus_db" { Floorplan "F:/my_design/hdlc/" "" "" { reset1 } "NODE_NAME" } "" } } { "F:/my_design/hdlc/hdlc.fld" "" { Floorplan "F:/my_design/hdlc/hdlc.fld" "" "" { reset1 } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 10 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 10" {  } { { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 13 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}