shift32.v

该工程是基于verilog hdl 语言编写的帧传输协议HDLC帧的发送端代码

module shift32(clk,en1,sel1,reset,crcout,clkout,flag,out);
parameter[31:0]d=32'b1110_0011_1110_0010_0101_0101_1111_1001;
input clk,reset,sel1,en1;
output clkout,crcout;
output flag,out;
reg dout,crcout;
reg[5:0]count1,count;
reg[15:0] crc_reg;
reg out;
integer j;
reg flag,next_flag;
reg[4:0] state,next_state;
parameter[4:0] e0=5'b00001;
parameter[4:0] e1=5'b00010;
parameter[4:0] e2=5'b00100;
parameter[4:0] e3=5'b01000;
parameter[4:0] e4=5'b10000;

always@(state or crcout) 
       begin
         next_state=e0;
         next_flag=1'b0;
       case(state)
         e0: begin
               if(crcout==1)
                  begin
                    next_state=e1;
                    next_flag=1'b0;
                  end
               else
                  begin
                    next_state=e0;
                    next_flag=1'b0;
                  end
             end
         e1: begin
               if(crcout==1)
                  begin
                    next_state=e2;
                    next_flag=1'b0;
                  end
               else
                  begin
                    next_state=e0;
                    next_flag=1'b0;
                  end
             end
         e2: begin
               if(crcout==1)
                  begin
                    next_state=e3;
                    next_flag=1'b0;
                  end
               else
                  begin
                    next_state=e0;
                    next_flag=1'b0;
                  end
            end
         e3: begin
               if(crcout==1)
                  begin
                    next_state=e4;
                    next_flag=1'b0;
                  end
               else
                  begin
                    next_state=e0;
                    next_flag=1'b0;
                  end
            end
         e4: begin
               if(crcout==1)
                  begin
                    next_state=e0;
                    next_flag=1'b1;
                  end
               else
                  begin
                    next_state=e0;
                    next_flag=1'b0;
                  end 
            end 
         
            default:begin
             
                   next_state=e0;
                   next_flag=1'b0;
                 end
              
     endcase
end
	
always@(posedge clk)
    begin
	if (en1) begin
      state<=next_state;
      flag<=next_flag;
    
	end
//test501 test(.clk(clk),.din(crcout),.flag(flag));
//tian0 tian(.din(crcout),.flag(flag),.out(out));
//assign clkout=clk&(~flag);


//always@(posedge clkout or posedge reset)
//begin
	if(clk && !flag && en1)begin
    if(reset)begin 
		count1=31;
		crc_reg<=16'hffff;
		count<=15;
		
	end
	
	else begin
		if(count>=0&&count<=31)begin
			dout=d[count1];
			count1<=count1-1;
		end
		else count1<=31;
	
	    if (sel1) begin
			crcout<=dout;
        	for(j=14;j>11;j=j-1) begin
				crc_reg[j+1]<=crc_reg[j];       
       		 end
        	crc_reg[12]<=crc_reg[11]^crc_reg[15]^dout;
        	for(j=10;j>4;j=j-1)begin
				crc_reg[j+1]<=crc_reg[j];       
        	end 
			crc_reg[5]<=crc_reg[4]^crc_reg[15]^dout;
			for(j=3;j>=0;j=j-1)begin
				crc_reg[j+1]<=crc_reg[j];       
        	end 
        	crc_reg[0]<=dout^crc_reg[15];
    	end
		else  begin     
			crcout<=crc_reg[count];
        	if(count>0)count<=count-1;
			else count<=15;
		end
    end
	end
end
always@(crcout or flag)
  begin
    if (flag==1) out<=1'b0;
    else out=crcout;
  end
endmodule