test501.v

该工程是基于verilog hdl 语言编写的帧传输协议HDLC帧的发送端代码

/////////////////////////////////////////
//test501模块是为检测5连1而做          //
//clk:全局时钟                         //
//din:输入信号                         //
//flag:5连1标志：1为检测到5连1         //
/////////////////////////////////////////

module test501(clk,din,flag);
input din,clk;
output flag;
reg flag,next_flag;
reg[4:0] state,next_state;
parameter[4:0] e0=5'b00001;
parameter[4:0] e1=5'b00010;
parameter[4:0] e2=5'b00100;
parameter[4:0] e3=5'b01000;
parameter[4:0] e4=5'b10000;

always@(state or din) 
       begin
         next_state=e0;
         next_flag=1'b0;
       case(state)
         e0: begin
               if(din==1)
                  begin
                    next_state=e1;
                    next_flag=1'b0;
                  end
               else
                  begin
                    next_state=e0;
                    next_flag=1'b0;
                  end
             end
         e1: begin
               if(din==1)
                  begin
                    next_state=e2;
                    next_flag=1'b0;
                  end
               else
                  begin
                    next_state=e0;
                    next_flag=1'b0;
                  end
             end
         e2: begin
               if(din==1)
                  begin
                    next_state=e3;
                    next_flag=1'b0;
                  end
               else
                  begin
                    next_state=e0;
                    next_flag=1'b0;
                  end
            end
         e3: begin
               if(din==1)
                  begin
                    next_state=e4;
                    next_flag=1'b0;
                  end
               else
                  begin
                    next_state=e0;
                    next_flag=1'b0;
                  end
            end
         e4: begin
               if(din==1)
                  begin
                    next_state=e0;
                    next_flag=1'b1;
                  end
               else
                  begin
                    next_state=e0;
                    next_flag=1'b0;
                  end 
            end 
         
            default:begin
             
                   next_state=e0;
                   next_flag=1'b0;
                 end
              
     endcase
end
always @(posedge clk)
begin
      state<=next_state;
      flag<=next_flag;
    end

endmodule