hdlc.v

该工程是基于verilog hdl 语言编写的帧传输协议HDLC帧的发送端代码

/*
flag1(en2,clk,dout);
free(clk,en3,dout);
shift32(clk,en1,sel1,reset,crcout,clkout,flag,out);
mux3(flag,free,signo,ept,sel2,dout);
//test501(clk,din,flag);
//tian0(din,flag,out);
control(clk,ept,rd,reset1,flag,en1,en2,en3,sel1,sel2);
//crc1(din,clk,en1,sel1,reset,crcout,clkout);
// shift32(clk,flag,sel1,reset,crcout,clkout);
*/
module hdlc(clk,reset1,ept,dout,dout1,dout2,dout3,dout4,din,flag,en1,en2,en3,sel1,sel2,sel3,clkout);
input clk,reset1,ept;
output dout,dout1,dout2,dout3,dout4,din,flag,en1,en2,en3,clkout;
output sel1,sel2,sel3;

shift32 shift(.clk(clk),.flag(flag),.sel1(sel1),.crcout(dout1),.reset(reset1),.clkout(clkout),.out(dout4),.en1(en1));
flag1 flag11(.en2(en2),.clk(clk),.dout(dout2));
free free1(.clk(clk),.en3(en3),.dout(dout3));
mux3 mux(.flag(dout2),.free(dout3),.signo(dout4),.ept(ept),.sel2(sel2),.dout(dout));

control control1(.clk(clk),.ept(ept),.rd(rd),.reset1(reset1),.flag(flag),.en1(en1),.en2(en2),.en3(en3),.sel1(sel1),.sel2(sel2));


endmodule