hdlc.map.rpt

该工程是基于verilog hdl 语言编写的帧传输协议HDLC帧的发送端代码

Info: Found 1 design units, including 1 entities, in source file crc1.v
    Info: Found entity 1: crc1
Warning: (10268) Verilog HDL information at control.v(27): Always Construct contains both blocking and non-blocking assignments
Info: Found 1 design units, including 1 entities, in source file control.v
    Info: Found entity 1: control
Info: Found 1 design units, including 1 entities, in source file flag1.v
    Info: Found entity 1: flag1
Info: Found 1 design units, including 1 entities, in source file mux3.v
    Info: Found entity 1: mux3
Warning: (10268) Verilog HDL information at free.v(14): Always Construct contains both blocking and non-blocking assignments
Info: Found 1 design units, including 1 entities, in source file free.v
    Info: Found entity 1: free
Info: Found 1 design units, including 1 entities, in source file test501.v
    Info: Found entity 1: test501
Info: Found 1 design units, including 1 entities, in source file tian0.v
    Info: Found entity 1: tian0
Warning: (10268) Verilog HDL information at shift32.v(94): Always Construct contains both blocking and non-blocking assignments
Warning: (10268) Verilog HDL information at shift32.v(146): Always Construct contains both blocking and non-blocking assignments
Info: Found 1 design units, including 1 entities, in source file shift32.v
    Info: Found entity 1: shift32
Info: Elaborating entity "hdlc" for the top level hierarchy
Warning: Output port "din" at hdlc.v(14) has no driver
Warning: Output port "sel3" at hdlc.v(15) has no driver
Info: Elaborating entity "shift32" for hierarchy "shift32:shift"
Warning: Verilog HDL assignment warning at shift32.v(110): truncated value with size 32 to match size of target (6)
Warning: Verilog HDL assignment warning at shift32.v(112): truncated value with size 32 to match size of target (6)
Warning: Verilog HDL assignment warning at shift32.v(119): truncated value with size 32 to match size of target (6)
Warning: Verilog HDL assignment warning at shift32.v(121): truncated value with size 32 to match size of target (6)
Warning: Verilog HDL assignment warning at shift32.v(140): truncated value with size 32 to match size of target (6)
Warning: Verilog HDL assignment warning at shift32.v(141): truncated value with size 32 to match size of target (6)
Warning: Output port "clkout" at shift32.v(4) has no driver
Info: Elaborating entity "flag1" for hierarchy "flag1:flag11"
Warning: Verilog HDL assignment warning at flag1.v(17): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at flag1.v(18): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at flag1.v(21): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at flag1.v(22): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at flag1.v(25): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at flag1.v(26): truncated value with size 32 to match size of target (1)
Info: Elaborating entity "free" for hierarchy "free:free1"
Warning: Verilog HDL assignment warning at free.v(19): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at free.v(22): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at free.v(23): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at free.v(29): truncated value with size 32 to match size of target (4)
Info: Elaborating entity "mux3" for hierarchy "mux3:mux"
Warning: Verilog HDL Always Construct warning at mux3.v(11): variable "dout" may not be assigned a new value in every possible path through the Always Construct.  Variable "dout" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Elaborating entity "control" for hierarchy "control:control1"
Info: (10035) Verilog HDL or VHDL information at control.v(8): object "j" declared but not used
Warning: Verilog HDL assignment warning at control.v(12): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL Always Construct warning at control.v(13): variable "ept" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL assignment warning at control.v(13): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL Always Construct warning at control.v(14): variable "ept" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL assignment warning at control.v(15): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at control.v(16): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL Always Construct warning at control.v(18): variable "ept" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL assignment warning at control.v(19): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at control.v(20): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at control.v(23): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at control.v(24): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL Always Construct warning at control.v(9): variable "en1" may not be assigned a new value in every possible path through the Always Construct.  Variable "en1" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at control.v(9): variable "en3" may not be assigned a new value in every possible path through the Always Construct.  Variable "en3" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL assignment warning at control.v(30): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at control.v(31): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at control.v(32): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at control.v(33): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at control.v(34): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at control.v(41): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at control.v(42): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at control.v(46): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at control.v(48): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at control.v(50): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at control.v(56): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at control.v(59): truncated value with size 32 to match size of target (6)
Warning: Verilog HDL assignment warning at control.v(61): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at control.v(65): truncated value with size 32 to match size of target (6)
Warning: Verilog HDL assignment warning at control.v(68): truncated value with size 32 to match size of target (6)
Warning: Verilog HDL assignment warning at control.v(70): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at control.v(85): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at control.v(87): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at control.v(88): truncated value with size 32 to match size of target (4)
Info: Power-up level of register "free:free1|d[7]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "free:free1|d[7]" with stuck data_in port to stuck value VCC
Warning: Reduced register "free:free1|d[6]" with stuck data_in port to stuck value GND
Info: Power-up level of register "free:free1|d[5]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "free:free1|d[5]" with stuck data_in port to stuck value VCC
Warning: Reduced register "free:free1|d[4]" with stuck data_in port to stuck value GND
Info: Power-up level of register "free:free1|d[3]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "free:free1|d[3]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "free:free1|d[2]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "free:free1|d[2]" with stuck data_in port to stuck value VCC
Warning: Reduced register "free:free1|d[1]" with stuck data_in port to stuck value GND
Info: Power-up level of register "free:free1|d[0]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "free:free1|d[0]" with stuck data_in port to stuck value VCC
Warning: LATCH primitive "mux3:mux|dout" is permanently enabled
Info: State machine "|hdlc|shift32:shift|state" contains 5 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine "|hdlc|shift32:shift|state"
Info: Encoding result for state machine "|hdlc|shift32:shift|state"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "shift32:shift|state.e4"
        Info: Encoded state bit "shift32:shift|state.e3"
        Info: Encoded state bit "shift32:shift|state.e2"
        Info: Encoded state bit "shift32:shift|state.e1"
        Info: Encoded state bit "shift32:shift|state.e0"
    Info: State "|hdlc|shift32:shift|state.e4" uses code string "00000"
    Info: State "|hdlc|shift32:shift|state.e3" uses code string "11000"
    Info: State "|hdlc|shift32:shift|state.e2" uses code string "10100"
    Info: State "|hdlc|shift32:shift|state.e1" uses code string "10010"
    Info: State "|hdlc|shift32:shift|state.e0" uses code string "10001"
Warning: Latch control:control1|en1 has unsafe behavior
    Warning: Ports ENA and PRE on the latch are fed by the same signal control:control1|always0~11
Warning: Latch control:control1|en3 has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal ept
Warning: Reduced register "flag1:flag11|count[3]" with stuck data_in port to stuck value GND
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "din" stuck at GND
    Warning: Pin "sel3" stuck at GND
    Warning: Pin "clkout" stuck at GND
Info: Implemented 142 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 14 output pins
    Info: Implemented 125 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 75 warnings
    Info: Processing ended: Sun Jul 01 22:51:42 2007
    Info: Elapsed time: 00:00:05