dtshow.vhd

用VHDL实现的DDS

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dtshow is
 port( 
      clr  : in std_logic;
    clk :in std_logic;
    cin1,cin2,cin3,cin4,cin5,cin6,cin7:in std_logic_vector(3 downto 0);
   decodeout :out std_logic_vector(6 downto 0);
    shumaguan :out std_logic_vector(6 downto 0)
);
end dtshow;
architecture behave of dtshow is
 component mux6 is
port(
    s :in std_logic_vector(2 downto 0);
    muxin1,muxin2,muxin3,muxin4 : in std_logic_vector(6 downto 0);
    y1,y2,y3,y4 : out std_logic
);
end component;
 component decode47 is port
  (
   adr :in std_logic_vector(3 downto 0);
  
   decodeout :out std_logic_vector(6 downto 0)
);
end component;
component conclk is port
(
   clk : in std_logic;
   clr :in std_logic;
   s   :buffer std_logic_vector(2 downto 0)
);
end component;
  signal y1,y2,y3,y4 	: std_logic;
  signal ss          	:std_logic_vector(2 downto 0);
  signal adress      	: std_logic_vector(3 downto 0);
  signal s1,s2,s3,s4 	:std_logic_vector(6 downto 0);
     begin
     adress<=y4&y3&y2&y1;

    s4<=cin1(3)&cin2(3)&cin3(3)&cin4(3)&cin5(3)&cin6(3)&cin7(3);
    s3<=cin1(2)&cin2(2)&cin3(2)&cin4(2)&cin5(2)&cin6(2)&cin7(2);
    s2<=cin1(1)&cin2(1)&cin3(1)&cin4(1)&cin5(1)&cin6(1)&cin7(1);
    s1<=cin1(0)&cin2(0)&cin3(0)&cin4(0)&cin5(0)&cin6(0)&cin7(0);


     u1: conclk port map(clk,clr,ss);
     u2: mux6   port map(ss,s1,s2,s3,s4,y1,y2,y3,y4);
     u3: decode47 port map(adress,decodeout);
       with ss select
          shumaguan<= "0000001"when"000",
                      "0000010"when"001",
                      "0000100"when"010",
                      "0001000"when"011",
          			  "0010000"when"100",
                      "0100000"when"101",
                      "1000000"when others;
 end behave;