reg16b.vhd

来自「用VHDL实现的DDS」· VHDL 代码 · 共 20 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity reg16B is
port(
     load : in std_logic;
     Din : in  std_logic_vector(15 downto 0);
     Dout : out std_logic_vector(15 downto 0)
);
end reg16B;
architecture behave of reg16B is
 begin 
    process(load)
    begin 
        if(load'event and load='1')then
             Dout<=Din;
		end if;
 end process;
end behave;