add9bit.vhd

来自「用VHDL实现的DDS」· VHDL 代码 · 共 21 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity add9bit is
 port( 
     clk  :in std_logic;
      op1 :in std_logic_vector(7 downto 0);
      op2 :in std_logic_vector(9 downto 0);
      result : out std_logic_vector(9 downto 0)
);
 end add9bit;
architecture behave of add9bit is
  begin 
    process(clk)
    begin 
            if(clk'event and clk='1')then
        result<=op1+op2;
       end if;
 end process;
   end behave;