date_shift.vhd

来自「用VHDL实现的DDS」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity date_shift is
port(
     clk : in std_logic;
     Din1,Din2,Din3,Din4,Din5,Din6,Din7 : in  std_logic_vector(3 downto 0);
     Dout1,Dout2,Dout3,Dout4,Dout5,Dout6,Dout7 : out std_logic_vector(3 downto 0)
);
end date_shift;
architecture behave of date_shift is
 begin 
    process(clk)
    begin 
        if(clk'event and clk='1')then
             Dout1<=Din1;
             Dout2<=Din2;
             Dout3<=Din3;
             Dout4<=Din4;
             Dout5<=Din5;
             Dout6<=Din6;
             Dout7<=Din7;
        		end if;
 end process;
end behave;