cnt8bit.vhd

来自「用VHDL实现的DDS」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 entity cnt8bit is
  port(
   en : in std_logic;
   nreset : in std_logic;
   clk :in std_logic;
   co  :out std_logic;
   qout : buffer std_logic_vector(7 downto 0));
end cnt8bit;
 architecture behave of cnt8bit is
  begin
     co<='1'when(qout="11111111") else '0';
    process(clk,nreset,en)
  begin 
     if(nreset='1')then
     qout<="00000000";
      elsif(nreset='0'and en='1')then
          qout<=qout;
    elsif(clk'event and clk='1')then
    qout<=qout+1;
 end if;

end process;
 end behave;