mux2.vhd

来自「用VHDL实现的DDS」· VHDL 代码 · 共 23 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mux2 is
port(
     sel :in std_logic;
     rom1 :in std_logic_vector(7 downto 0);
     rom2 :in std_logic_vector(7 downto 0);
     ad_date :out std_logic_vector(7 downto 0)
);
end mux2;
architecture behave of mux2 is
 begin 
   process(sel,rom1,rom2)
     begin
          if(sel='1')then
            ad_date<=rom1;
           else 
             ad_date<=rom2;
          end if;
       end process;
end behave;