fenpin.vhd

来自「用VHDL实现的DDS」· VHDL 代码 · 共 29 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenpin is
port
(    nreset  :in std_logic;
     clk  :in std_logic; 
     fc   :out std_logic;
     wr  :out std_logic;
    qcnt:buffer std_logic_vector(4 downto 0));
end fenpin;
architecture behave of fenpin is
 begin 
  
 process(clk,nreset)
      begin 
          if(nreset='1') then
          qcnt<="00000";
          elsif(clk'event and clk='1')  then            
                     qcnt<=qcnt+1;
               end if;
      if qcnt="00101" then wr<='0';
       else wr<='1';
      end if;
   fc<=qcnt(4);
    end process;
    End behave;