cntm10.vhd

来自「用VHDL实现的DDS」· VHDL 代码 · 共 32 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cntm10 is
 port(
    clear : in std_logic;
    ci :in std_logic;
    clk :in std_logic;
    co :out std_logic;
    qout : buffer std_logic_vector(3 downto 0)
);
end cntm10;
architecture behave of cntm10 is
  begin 
    co<='1'when(qout="1001"and ci='1') else '0';
  
  process(clk,clear)
    begin
      if(clear='1')then
              qout<="0000";
        elsif(clk'event and clk='1')then
         if(ci='1')then
            if(qout="1001") then 
                qout<="0000";

         else qout<=qout+1;
      end if;
    end if;
  end if;
   end process;
end behave;