decode47.vhd

来自「用VHDL实现的DDS」· VHDL 代码 · 共 28 行

library ieee;
use ieee.std_logic_1164.all;
 entity decode47 is port
  (
     adr :in std_logic_vector(3 downto 0);
     decodeout :out std_logic_vector(6 downto 0)
);
end decode47;
 architecture behave of decode47 is
   begin
  process(adr)
    begin 
    
case adr is
   when"0000"=>decodeout<="1111110";
   when"0001"=>decodeout<="0110000";
   when"0010"=>decodeout<="1101101";
   when"0011"=>decodeout<="1111001";
   when"0100"=>decodeout<="0110011";
   when"0101"=>decodeout<="1011011";
   when"0110"=>decodeout<="1011111";
   when"0111"=>decodeout<="1110000";
   when"1000"=>decodeout<="1111111";
   when others=>decodeout<="1111011";
 end case;
 end process;
end behave;