datechange.vhd

来自「用VHDL实现的DDS」· VHDL 代码 · 共 23 行

library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
entity datechange is
 port(
    date : in std_logic;
    romdate :in std_logic_vector(7 downto 0);
    lastdate : out std_logic_vector(7 downto 0)
);
end datechange;
architecture behave of datechange is
  begin 
     process(date,romdate)
    begin
        if(date='1')then
          lastdate<=not romdate;
        else 
           lastdate<= romdate;
  end if;
    end process;
 end behave;