dff.vhd

用VHDL实现的DDS

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity dff is
   port(d          :in std_logic_vector(7 downto 0);
        clk         :in std_logic;
         q       :out std_logic_vector(7 downto 0)
       );
end dff;

architecture behave of dff is
   signal  temp:std_logic_vector(7 downto 0);

begin
 process(clk)
   begin
        if (clk='1'and clk'event)then
           temp<=d;
           end if;
           end process;
          q<=temp;
        end behave;