test_fre.vhd

用VHDL实现的DDS

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity test_fre is
 port(
    clk : in std_logic;  
    ck : in std_logic; -- 待测信号
    out1,out2,out3,out4 : out std_logic_vector(3 downto 0)
);
end test_fre;
architecture behave of test_fre is 
 
   component cntm10 is
   port(
    clear :in std_logic;
    ci :in std_logic;
    clk :in std_logic;
    co :out std_logic;
    qout : buffer std_logic_vector(3 downto 0)
);
end component;
component divclk is
  port 
( clk :in std_logic;
  testen :out std_logic;
  load :out std_logic;
  clr_cnt :out std_logic
);
end component;
 component reg16B is
  port(
     load : in std_logic;
     Din : in  std_logic_vector(15 downto 0);
     Dout : out std_logic_vector(15 downto 0)
);
end component;
signal tsten :std_logic;
signal ld :std_logic;
signal clr :std_logic;
signal co1 :std_logic;
signal co2 :std_logic;
signal co3 :std_logic;
signal co4 :std_logic;
signal ot1 :std_logic_vector(3 downto 0);
signal ot2 :std_logic_vector(3 downto 0);
signal ot3 :std_logic_vector(3 downto 0);
signal ot4 :std_logic_vector(3 downto 0);
signal din :std_logic_vector(15 downto 0);
signal dout :std_logic_vector(15 downto 0);
begin 
   u0: divclk port map(clk,tsten,ld,clr);
   u1: cntm10 port map(clr,tsten,ck,co1,ot1);
   u2: cntm10 port map(clr,co1,ck,co2,ot2);
   u3: cntm10 port map(clr,co2,ck,co3,ot3);
   u4: cntm10 port map(clr,co3,ck,co4,ot4);
   din<=ot4&ot3&ot2&ot1;
   u5: reg16B port map(ld,din,dout);
    out1<=dout(3 downto 0);
    out2<=dout(7 downto 4);
    out3<=dout(11 downto 8);
    out4<=dout(15 downto 12);
end behave;