代码搜索结果
找到约 7,641 项符合
V 的代码
lwbdecode.v
/////////////////////////////////////////////////////////////////////
//// ////
//// LWB rev 1.2 -- Memory Address Decode
execution.v
`timescale 1ns/10ps
module execution(clk, reset, instruction_decode_bus, execution_bus, execution_destination);
input clk;
input reset;
input[107:0] instruction_decode_bus;
output[75:0] exe
memory_access.v
`timescale 1ns/10ps
module memory_access(clk, reset, execution_bus, memory_bus, memory_destination);
input clk;
input reset;
input[75:0] execution_bus;
output[75:0] memory_bus;
output[4:0
register_file.v
module register_file(clk, addr1, out1, addr2, out2, write_enable, write_addr, write_value); //32 general 32-bit registers
input clk;
input[4:0] addr1; //address of 32 registers, 5 bits needed
flopr.v
module flopr //flip-flop
#(parameter WIDTH = 8)
(
input clk, reset,
input [WIDTH-1:0] d,
output reg[WIDTH-1:0] q
);
always@(posedge clk, posedge reset)
begin
if(reset)
data_memory.v
module data_memory(clk, read_addr, out, write_enable, write_addr, write_value); //it's a ram
inout clk;
input[31:0] read_addr;
output reg[31:0] out;
input write_enable;
input[31:0] write_ad
write_back.v
`timescale 1ns/10ps
module write_back(clk, reset, memory_bus, write_back_bus, write_back_destination);
input clk;
input reset;
input[75:0] memory_bus;
output[37:0] write_back_bus;
output[
instruction_fetch.v
`timescale 1ns/10ps
module instruction_fetch(clk, reset, instruction, branch_bus, execution_destination, memory_destination, write_back_destination);
input clk;
input reset;
output reg[31:0]
pipelinedcpu.v
`timescale 1ns/10ps
module pipelinedCPU(clk, reset);
input clk;
input reset;
wire[31:0] instruction1, instruction2;
wire[33:0] branch_bus1, branch_bus2;
wire[107:0] instruction_decode_
instruction_decode.v
`timescale 1ns/10ps
module instruction_decode(clk, reset, instruction, execution_destination, memory_destination, write_back_destination, write_back_bus, branch_bus, instruction_decode_bus);
inpu