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V 的代码
sync_check.v
`timescale 1ns / 10ps
`include "vga_defines.v"
module sync_check( pclk, rst, enable, hsync, vsync, csync, blanc,
hpol, vpol, cpol, bpol,
thsync, thgdel, thgate, thlen,
tvsync, tvgd
vga_csm_pb.v
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
module vga_csm_pb (clk_i, req0_i, ack0_o, adr0_i, dat0_i, dat0_o, we0_i, req1_i, ack1_o, adr1_i, dat1_i, dat1_o, we1_i);
wb_model_defines.v
`timescale 1ns / 10ps
//`timescale 1ns / 1ns
vga_cur_cregs.v
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
module vga_cur_cregs (
clk_i, rst_i, arst_i,
hsel_i, hadr_i, hwe_i, hdat_i, hdat_o, hack_o,
cadr_i, cdat_o
);
test_bench_top.v
`timescale 1ns/10ps
module test;
reg clk;
reg rst;
parameter LINE_FIFO_AWIDTH = 7;
wire int;
wire [31:0] wb_addr_o;
wire [31:0] wb_data_i;
wire [31:0] wb_data_o;
wire [3:0] wb_
vga_clkgen.v
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
`include "vga_defines.v"
module vga_clkgen (
pclk_i, rst_i, pclk_o, dvi_pclk_p_o, dvi_pclk_m_o, pclk_ena_o
);
/
wb_b3_check.v
module wb_b3_check (clk_i, cyc_i, stb_i, we_i, cti_i, bte_i, ack_i, err_i, rty_i);
input clk_i;
input cyc_i;
input stb_i;
input [2:0] cti_i;
input [1:0] bte_i;
input
tests.v
task show_errors;
begin
$display("\n");
$display(" +--------------------+");
$display(" | Total ERRORS: %0d |", error_cnt);
$display(" +----------
vga_enh_top.v
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
`include "vga_defines.v"
module vga_enh_top (
wb_clk_i, wb_rst_i, rst_i, wb_inta_o,
wbs_adr_i, wbs_dat_i, wbs_dat_o,
vga_pgen.v
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
`include "vga_defines.v"
module vga_pgen (
clk_i, ctrl_ven, ctrl_HSyncL, Thsync, Thgdel, Thgate, Thlen,
ctrl_VSync