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// synopsys translate_off `include "timescale.v" // synopsys translate_on `include "can_defines.v" module can_acf ( clk, rst, id, /* Mode register */ reset_mode, acce

// synopsys translate_off `include "timescale.v" // synopsys translate_on `include "can_defines.v" module can_fifo ( clk, rst, wr, data_in, addr, data_out, fifo_sele

// synopsys translate_off `include "timescale.v" // synopsys translate_on `include "can_defines.v" module can_top ( `ifdef CAN_WISHBONE_IF wb_clk_i, wb_rst_i, wb_dat_i,

// synopsys translate_off `include "timescale.v" // synopsys translate_on `include "can_defines.v" module can_btl ( clk, rst, rx, /* Mode register */ reset_mode, /* Bus

// synopsys translate_off `include "timescale.v" // synopsys translate_on `include "can_defines.v" module can_bsp ( clk, rst, sample_point, sampled_bit, sampled_bit_q, tx

// synopsys translate_off `include "timescale.v" // synopsys translate_on module can_register_asyn ( data_in, data_out, we, clk, rst ); parameter WIDTH = 8; // default parame

// synopsys translate_off `include "timescale.v" // synopsys translate_on `include "can_defines.v" `include "can_testbench_defines.v" module can_testbench(); parameter Tp = 1; paramet

/* Mode register */ `define CAN_MODE_RESET 1'h1 /* Reset mode */ /* Bit Timing 0 register value */ `define CAN_TIMING0_BRP 6'h1 /* Baud rate prescaler (2*

// synopsys translate_off `include "timescale.v" // synopsys translate_on module can_register_asyn_syn ( data_in, data_out, we, clk, rst, rst_sync ); parameter WIDTH = 8;

// synopsys translate_off `include "timescale.v" // synopsys translate_on module can_register ( data_in, data_out, we, clk ); parameter WIDTH = 8; // default parameter of the re