代码搜索结果

// synopsys translate_off `include "timescale.v" // synopsys translate_on module can_crc (clk, data, enable, initialize, crc); parameter Tp = 1; input clk; input data;

// Uncomment following line if you want to use WISHBONE interface. Otherwise // 8051 interface is used. // `define CAN_WISHBONE_IF // Uncomment following line if you want to use CAN in Ac

// synopsys translate_off `include "timescale.v" // synopsys translate_on module can_register_syn ( data_in, data_out, we, clk, rst_sync ); parameter WIDTH = 8; // default

`define VENDOR_FPGA // // enable / disable 12bit DVI output // (for use with external DVI transmitters) `define VGA_12BIT_DVI //////////////////////// // // Hardware Cursors // //

//synopsys translate_off `include "timescale.v" //synopsys translate_on module vga_tgen( clk, clk_ena, rst, Thsync, Thgdel, Thgate, Thlen, Tvsync, Tvgdel, Tvgate, Tvlen, eol, eof, gate, h

//synopsys translate_off `include "timescale.v" //synopsys translate_on module vga_vtim(clk, ena, rst, Tsync, Tgdel, Tgate, Tlen, Sync, Gate, Done); // inputs & outputs input clk; // mast

//synopsys translate_off `include "timescale.v" //synopsys translate_on // set FIFO_RW_CHECK to prevent writing to a full and reading from an empty FIFO //`define FIFO_RW_CHECK // Long Ps

`timescale 1ns / 10ps

//synopsys translate_off `include "timescale.v" //synopsys translate_on module vga_fifo_dc (rclk, wclk, aclr, wreq, d, rreq, q, rd_empty, rd_full, wr_empty, wr_full); // parameters parame

//synopsys translate_off `include "timescale.v" //synopsys translate_on module vga_curproc (clk, rst_i, Thgate, Tvgate, idat, idat_wreq, cursor_xy, cursor_en, cursor_res, cursor_wadr, cur