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tb_eth_defines.v
//`define VERBOSE // if log files of device modules are written
`define MULTICAST_XFR 0
`define UNICAST_XFR 1
`define BROADCAST_XFR 2
`
eth_crc.v
`include "timescale.v"
module eth_crc (Clk, Reset, Data, Enable, Initialize, Crc, CrcError);
parameter Tp = 1;
input Clk;
input Reset;
input [3:0] Data;
input Enable;
input Initiali
tb_ethernet_with_cop.v
//
`include "tb_eth_defines.v"
`include "eth_defines.v"
`include "timescale.v"
module tb_ethernet_with_cop();
parameter Tp = 1;
reg wb_clk_o;
reg wb_rst_o;
eth_transmitcontrol.v
`include "timescale.v"
module eth_transmitcontrol (MTxClk, TxReset, TxUsedDataIn, TxUsedDataOut, TxDoneIn, TxAbortIn,
TxStartFrmIn, TPauseRq, TxUsedDataOutDete
eth_txstatem.v
`include "timescale.v"
module eth_txstatem (MTxClk, Reset, ExcessiveDefer, CarrierSense, NibCnt, IPGT, IPGR1,
IPGR2, FullD, TxStartFrm, TxEndFrm, TxUnderRun, Collis
eth_macstatus.v
//
`include "timescale.v"
module eth_macstatus(
MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError,
MRxErr, MRxDV, RxS
wb_model_defines.v
// WISHBONE frequency in GHz
`define WB_FREQ 0.100
// memory frequency in GHz
`define MEM_FREQ 0.100
// setup and hold time definitions for WISHBONE - used in BFMs for signal generation
`
wb_bus_mon.v
`include "timescale.v"
`include "wb_model_defines.v"
// WISHBONE bus monitor module - it connects to WISHBONE master signals and
// monitors for any illegal combinations appearing on the bus.
eth_registers.v
`include "eth_defines.v"
`include "timescale.v"
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
eth_random.v
`include "timescale.v"
module eth_random (MTxClk, Reset, StateJam, StateJam_q, RetryCnt, NibCnt, ByteCnt,
RandomEq0, RandomEqByteCnt);
parameter Tp = 1;
input MTxClk;