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找到约 7,641 项符合
V 的代码
lcd_clk.v
/***************************************************************************************
** Module Name: LCD_CLK
** Descriptions: create lcd clk about 500HZ delay time 2ms
** wave figure:________
rcvr.v
/******************************************************************************
*
* File Name: rcvr.v
* Version: 1.1
* Date: January 22, 2000
* Model: Receiver Chip
*
*
txmit_tf.v
`timescale 1 ns / 1 ns
// TOOL: Project Navigator
// DATE: Fri Apr 14 14:26:16 2000
// TITLE:
// MODULE: txmit
// DESIGN: txmit
// FILENAME: txmit
// PROJECT: transmit
//
rcvr_tf.v
`timescale 1 ns / 1 ns
// TOOL: Project Navigator
// DATE: Fri Apr 14 17:32:41 2000
// TITLE:
// MODULE: rcvr
// DESIGN: rcvr
// FILENAME: rcvr
// PROJECT: receive
// VERS
uart.v
/******************************************************************************
*
* File Name: uart.v
* Version: 1.1
* Date: January 22, 2000
* Model: Uart Chip
* Dependenci
txmit.v
/******************************************************************************
*
* File Name: txmit.v
* Version: 1.1
* Date: January 22, 2000
* Model: Uart Chip
*
* Co
wb_slave_behavioral.v
`include "timescale.v"
`include "wb_model_defines.v"
module WB_SLAVE_BEHAVIORAL
(
CLK_I,
RST_I,
ACK_O,
ADR_I,
CYC_I,
DAT_O,
DAT_I,
ERR_O,
RTY_O,
SEL_I,
STB_I,
WE_I,
CA
eth_receivecontrol.v
`include "timescale.v"
module eth_receivecontrol (MTxClk, MRxClk, TxReset, RxReset, RxData, RxValid, RxStartFrm,
RxEndFrm, RxFlow, ReceiveEnd, MAC, DlyCrcEn, TxDo
timescale.v
`timescale 1ns / 1ns