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if.v
//******************************************************************************
//
// IF.v
//
// Calculates the next PC and retrieves the instruction from memory
//
//
//*********************
a.v
module adc(clk,rst,convst,busy_adc);
input clk,rst,convst;
inout busy_adc;
reg busy_adcbuf;
assign busy_adc=busy_adcbuf;
always@(posedge clk or negedge rst)
begin
if(!rst)busy_adcbuf
and_or.v
module and_or (clk, resetn, and_test, or_test);
input clk, resetn, and_test, or_test;
reg a;
reg [3:0] b;
reg [3:0] c;
reg [3:0] d;
reg [3:0] e;
reg [3:0] g;
always @ (posedge cl
as.v
module as(Z,A,B,C,D,E,F,G,H,TEMP1,TEMP2);
input A,B,C,D,E,F,G,H;
output TEMP1,TEMP2,Z;
wire [7:0] TEMP1;
wire [11:0] TEMP2;
and x1(TEMP1[0],A,B);
or x2(TEMP1[1],C,D);
//and x3(TEMP1[2],E,F);
makefile,v
head 1.1;
access;
symbols;
locks
dls:1.1; strict;
comment @# @;
1.1
date 97.09.21.19.31.19; author dls; state Dist;
branches;
next ;
desc
@@
1.1
log
@pre-3e code
@
text
@#
# Make the Xinu vers
makefile,v
head 1.1;
access;
symbols;
locks
jaf:1.1; strict;
comment @# @;
1.1
date 96.02.13.22.50.30; author jaf; state Exp;
branches;
next ;
desc
@@
1.1
log
@Initial revision
@
text
@#
# $Log$
#
###
makefile,v
head 1.1;
access ;
symbols ;
locks ; strict;
comment @# @;
1.1
date 86.06.25.12.51.27; author jqj; state Exp;
branches ;
next ;
desc
@@
1.1
log
@Initial revision
@
text
@CF
makefile,v
head 1.1;
access ;
symbols ;
locks ; strict;
comment @# @;
1.1
date 86.06.25.12.51.07; author jqj; state Exp;
branches ;
next ;
desc
@@
1.1
log
@Initial revision
@
text
@CF
makefile,v
head 1.1;
access ;
symbols ;
locks ; strict;
comment @# @;
1.1
date 86.06.25.12.51.04; author jqj; state Exp;
branches ;
next ;
desc
@@
1.1
log
@Initial revision
@
text
@CF
makefile,v
head 1.1;
access ;
symbols ;
locks ; strict;
comment @# @;
1.1
date 86.06.25.12.51.33; author jqj; state Exp;
branches ;
next ;
desc
@@
1.1
log
@Initial revision
@
text
@#