and_or.v

veilog 代码 用户可以直接调用

module and_or (clk, resetn, and_test, or_test);
	input		clk, resetn, and_test, or_test;
	reg 		a;
	reg [3:0]	b;
	reg [3:0]	c;
	reg [3:0]	d;
	reg [3:0]	e;
	reg [3:0]	g;
	
	always @ (posedge clk or negedge resetn)
	begin
	if (~resetn)	// Active low asynchronous reset.
		begin

		a	<=	0;
		b	<=	4'd4; 	// Bad form to async set values
//  like this, should be a
//  parameter.
		c	<=	4'd5; 
		d	<=	0;
		e	<=	0;
		g	<=	0;
		end

		else if (and_test)
		begin

	d 	<= 	(c && !a); 	// d gets assigned value of 0.
	e	<=	(c & !a); 	// e gets assigned value of
//  1010.	
	g	<=	(b & c); 	// g gets assigned the value
//  0100.
		end
	else if (or_test == 1)	// Equivalent to simply (or_test).
	begin
	
	e	<=	(c | !a); 	// e gets assigned value of all
//  1's (1111).	
	g	<=	(b | c); 	// g gets assigned the value 0101.
	end
		else
		begin
	d 	<= 	0; 	// Assign default values to avoid
//  unwanted latches.
	e	<=	0; 
	g	<=	0;  
		end
	end
	endmodule