if.v

来自「用VHDL设计具有简单MIPS功能的源码」· Verilog 代码 · 共 52 行

//******************************************************************************
//
// IF.v
//
// Calculates the next PC and retrieves the instruction from memory
// 
//
//******************************************************************************

module IF (
	// Outputs
	pc, instr,
	// Inputs
	clk,  rst, Branch, WritePC, BranchAddr
);

	input 		clk, rst;
	input		Branch, WritePC;
	input[31:0] BranchAddr;
	output [31:0]	instr;		// current instruction
	output [31:0]	pc;			// address of instruction
  
	reg [31:0]	pc;			// program counter
	wire [31:0] address;

//******************************************************************************
// calculate the next PC
//******************************************************************************
//	wire Bra;
	always @(posedge clk) 
	begin
		if(rst)
			pc <= 32'b0;
		else if (WritePC) 
		begin
			if(Branch)
				pc <= BranchAddr+4;
			else
				pc <= pc + 4;
		end 
		else
			pc <= pc;
	end

//******************************************************************************
// instruction memory instantiation
//******************************************************************************
//	assign Bra = rst?0:Branch;
	assign address = rst?0:(Branch?BranchAddr:pc);
	instrmem lpm_rom_inst(.address(address[5:2]), .clock(clk), .q(instr));

endmodule