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`include "timescale.v" module i2c_slave_model (scl, sda); // // parameters // parameter I2C_ADR = 7'b001_0000; // // input && outpus // input scl; inout sda; // // V

S // synopsys translate_off `include "timescale.v" // synopsys translate_on `include "i2c_master_defines.v" module i2c_master_top( wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_

`include "timescale.v" module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty); parameter dwidth = 32; parameter awidth = 32; input clk, rst; output [aw

// I2C registers wishbone addresses // bitcontroller states `define I2C_CMD_NOP 4'b0000 `define I2C_CMD_START 4'b0001 `define I2C_CMD_STOP 4'b0010 `define I2C_CMD_WRITE 4'b0100 `define I2C_CMD_

// ///////////////////////////////////// // Bit controller section ///////////////////////////////////// // // Translate simple commands into SCL/SDA transitions // Each command has 5 states, A/B/C/

`timescale 1ns / 10ps

`include "timescale.v" module tst_saa7113 (error,dsprst,xreset,saareset,ARDY,ED_O,ED_OEN_O,SRAM_1_EA,SRAM_2_EA,SRAM_1_O_ED,SRAM_2_O_ED); //REGS reg reset; reg clk;//50MHz reg llck;//here

///////////////////////////////////////////////////////////////////// //// //// //// LWB rev 1.2 -- SAA7113 Control Logic

///////////////////////////////////////////////////////////////////// //// //// //// LWB rev 1.2 -- BUS CHANGE FOR TWO SRAMS

///////////////////////////////////////////////////////////////////// //// //// //// LWB rev 1.2 -- SRAM INTERFACE